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Artix 7


Prashik

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The Nexys4 DDR board contains 240 DSP slices within its FPGA.  These are embedded within the FPGA chip, and are discussed further in the Xilinx user guide--although the one I found googling quickly was for Virtex-6 chips.  There are two ways to use these slices: 1) by relying on the Xilinx tools (Vivado) to infer them from your verilog source code, and 2) by instantiating their functionality explicitly via the components within the libraries guide.

I've personally allowed Vivado to infer them, and not needed to use the libraries guide.  You can find my work using them in this double-clocked FFT core--and FFT that accepts and produces two complex samples per clock.  The FFT can be both configured to use, and not to use, the DSP slices based upon what you have available.

If you are still interested in the schematic, you can find a link to the schematic on the resources page for the Nexys-4 DDR (assuming that's the Nexys 4 you are referencing ...), as well as links to examples and master constraint files.

Dan

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