zygot

Transceiver Boot Camp

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Hi @zygot,

I just downloaded your zip and started to look through the documentation. I stopped a bit to the board review you made for the Genesys 2 and I wanted to talk with you about that. First of all thanks for the good points. The engineer who worked for the FMC was very pleased that it was appreciated. I want to focus a bit on the bad points and see what we can fix.:

1.  Manual full of errors: I didn't see anywhere to have errors reported. If you saw things that are not technically correct or are misleading please let us know what they are

2. Incomplete schematics. I agree with you on this part. Unfortunately, it's not Digilent's decision to do that so we can't do much about that

3. Incomplete constraints file: That can't be right. All the pins should be listed. If you found something missing, please let us know.

4. Yes, the SDK support was a bit delayed and we're sorry about that.

5. The wimpy power supply. I'm not sure what you mean by that. I'm not sure how would be better if the power supply will get to its limitations from simple designs. We want to improve the power supplies and some details would help us bring better products.

If you can elaborate the problems you found by working with the board would be great. I already tried to find previous post about them on the forum and I saw that you addressed the DPTI problem and it took 5-6 months until my colleagues could provide the support.. 

Best regards,

Bianca

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Bianca,

Thanks for the note. It's nice to know that someone is taking the time to read through the project documentation.

As to the constraints file for the Genesys2. You are the second Digilent person to respond to this ( Tom posted and then removed his post...). I just checked the GIT repository to view the latest Genesys2 xdc file. I have bad eyesight too but you should read through my transceiver project constraints file:

set_property -dict { PACKAGE_PIN C8 } [get_ports { GTXQ3_P }]; # DISPLY_CLK_P
set_property -dict { PACKAGE_PIN C7 } [get_ports { GTXQ3_N }]; # DISPLY_CLK_N
set_property -dict { PACKAGE_PIN E4 } [get_ports { RXP[0] }]; # RX_LANE0_P
set_property -dict { PACKAGE_PIN E3 } [get_ports { RXN[0] }]; # RX_LANE0_N
set_property -dict { PACKAGE_PIN D6 } [get_ports { RXP[1] }]; # RX_LANE1_P
set_property -dict { PACKAGE_PIN D5 } [get_ports { RXN[1] }]; # RX_LANE1_N
set_property -dict { PACKAGE_PIN B6 } [get_ports { RXP[2] }]; # RX_LANE2_P
set_property -dict { PACKAGE_PIN B5 } [get_ports { RXN[2] }]; # RX_LANE2_N
set_property -dict { PACKAGE_PIN A8 } [get_ports { RXP[3] }]; # RX_LANE3_P
set_property -dict { PACKAGE_PIN A7 } [get_ports { RXN[3] }]; # RX_LANE3_N
set_property -dict { PACKAGE_PIN D2 } [get_ports { TXP[0] }]; # TX_LANE0_P
set_property -dict { PACKAGE_PIN D1 } [get_ports { TXN[0] }]; # TX_LANE0_N
set_property -dict { PACKAGE_PIN C4 } [get_ports { TXP[1] }]; # TX_LANE1_P
set_property -dict { PACKAGE_PIN C3 } [get_ports { TXN[1] }]; # TX_LANE1_N
set_property -dict { PACKAGE_PIN B2 } [get_ports { TXP[2] }]; # TX_LANE2_P
set_property -dict { PACKAGE_PIN B1 } [get_ports { TXN[2] }]; # TX_LANE2_N
set_property -dict { PACKAGE_PIN A4 } [get_ports { TXP[3] }]; # TX_LANE3_P
set_property -dict { PACKAGE_PIN A3 } [get_ports { TXN[3] }]; # TX_LANE3_N


Do you or Tom see any of these pins in the "official" constraints file? I don't. You have pin assignments for all of the DisplayPort auxiliary pins but none of the IO bank 118 pins. These are the only mDP pins that I use in the project by the way.

When I post complaints about my negative Digilent experiences it only because I want Digilent to have excellent products and support so that I can continue to you use as a vendor. I would hope that every employee of Digilent wants the same thing. I won't hesitate to make known my positive experiences to help you proceed that direction. 

Merry Christmas to all!

 

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Thanks Zygot,

That's what we want too and that's why we want to hear the bad things we do, so we can correct them in the future, but we also love to hear the positive ones. Maybe after Christmas you can give me a hit about the power supplies. The engineer who designed them is very curious about them. 

Regarding the XDC, these are not simply IO pins, in order to use them you have to use the GT primitive. Once you instantiate the MIG with the wizard there is no need to have them in the XDC too because the wizard creates its own XDC. That was the main reason for not putting them there. It gives the pinout in the reference manual and then it guides you to the Xilinx documentation that shows you how to instantiate them with the wizard. 

Merry Christmas to you too!

Edited by Bianca

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Bianca,

Your boss should have let you start Christmas vacation before you're last post... hopefully you won't be replying to this one till next week. My boss (me) is a real Grinch so I'm still working even today.

"Regarding the XDC, these are not simply IO pins, in order to use them you have to use the GT primitive. Once you instantiate the MIG with the wizard there is no need to have them in the XDC too because the wizard creates its own XDC. That was the main reason for not putting them there. It gives the pinout in the reference manual and then it guides you to the Xilinx documentation that shows you how to instantiate them with the wizard. "

I disagree with every statement and conclusion in that sentence.

MIG? Do you mean the external Memory Interface Generator? I've used this tool quite a few times to create DDR controllers. There's no MIG in this project. Seems to me that you are an ideal candidate for the Transceiver Boot Camp. Someone at Digilent surely has an Xilinx FMC Debug board. If not, convince the boss to make a huge $160 capital investment for the good of all. Once you complete the project please do find the xdc file buried in the Xilinx source that assigned pins to the GTX transceiver IO and enlighten me. Create a new project but comment out my assignments to these pins and see what you get.

Now that you've mentioned the MIG you reminded me of a complaint with the Genesys2; The FPGA on board deserves a nice 64-bit DDR3 memory or better yet a 128-bit DDR3 memory not a 32-bit one. This is a bottleneck for designs that I'd like to do on the board. Add that to the BAD section. Also, I still want the DDR pins listed in the xdc file so that I can use the MIG wizard without having to reference the schematic.

Before discussing the Genesys2 power supply why don't we deal with that horrible User's Manual. Obviously, someone took the Nexys Video User's Manual and started to cut and paste names without actually looking at the pin assignments in the pictures of the various interfaces. Please ask someone to create a Genesys2 User's Manual without all of those errors.

Perhaps you'd care to enter the Differential PMOD challenge as well. You might find it interesting.

and a Happy New Year to us all

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@zygot,

Well it looks I'm still here but not because my boss didn't let me in vacation but because I'm a little Grinch myself and I wanted to stay a bit more. It is in our interest to change the manual if there are errors in it. It is true that some parts are copy/paste from nexys video when the configuration is the same.

You said that you disagree with me regarding my sentence because you didn't use the MIG. You used the Aurora IP and in the same way the pins are instantiate for the GT. And the XDC is generated from there. Please look at the picture below. Isn't this how you instantiate your pins?

aurora_gt_selection.png 

 

Bianca

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D@n,

Just pull up the schematic and then the on-line Genesys2 User's Manual... now start comparing the two. Am I the only person to have done this? If you find matching documents please post both pdf files.

Bianca,

Did you build the project with my GTX pin locations commented out and get the correct pin assignments? I've looked for an xdc file in Xilinx example generated code and haven't found one assigning the pin locations. There are some timing constraints there. In my experience with the MIG you have to check every pin assignment against the schematic which is why I'd like to see them in the released xdc file from Digilent. Perhaps I'm not trusting enough to assume that unconstrained IO are assigned properly by Vivado. I haven't tried to build the project without specifying the GTX pins in my toplevel constraints file... Guess I have to try doing that. I still fail to see the logic in NOT including every pin in your master constraints file. I do know that what I did for this project does work. In fact, it would be a good check for errors in setting up the respective "wizard" tools. Even wizards don't prevent us from creating [problems

BTW you have selected the wrong GTX quad for the Genesys2 board in the picture you posted.

And.. all of us need to get out more....

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Zygot,

I'll address the problem with the XDC and the pins for the future boards to see what my colleagues, that are responsible for this, might think about that. I'll have someone to look at the user manual too.

Regards,

Bianca

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