clock Create customized clock using counters

[Saad Bin Shafique]

Hi. I want to generate 15MHz clock from 40MHz system clock. I could use DCM to generate this clock but i want to use counter for that purpose. Can someone tell me that how can i do that?

[Sergiu]

Hello,

Since 40 / 15 = 2.(6) which is not an integer, you will have to divide by 8 (to get 5) and multiply by 3, which is exactly what the MMCM does. Dividing by 8 is easy however multiplying the frequency is not and I am not sure that it is even possible. Here is a trick used for doubling the frequency however the signal it generates does not have a 50% duty cycle which can cause problems later on. http://vhdlguru.blogspot.ro/2010/04/combinatorial-frequency-multiplier.html

My advice, use the MMCM.

Sergiu

[D@n]

If you don't mind the phase noise, you could take an 8-bit counter and add 3 to it on every clock, then use the most significant bit.

Dan

[hamster]

On 12/6/2016 at 0:00 AM, D@n said:

If you don't mind the phase noise, you could take an 8-bit counter and add 3 to it on every clock, then use the most significant bit.

Dan

Dan meant a 'three bit' counter (that counts from zero to seven). when you adding 3 each cycle the counter will run as follows:

0, 3, 6, 1, 4, 7, 2, 5,  0, 3, 6, 1, 4, 7, 2, 5...

And the most significant bit of the counter will be:

0, 0, 1, 0, 1, 1, 0 ,1, 0, 0, 1, 0, 1, 1, 0 ,1...

That gives three 0-to-1 transitions every eight clock ticks, for  a total of 15,000,000 every second if you are using a 40MHz clock.

You can do the same thing with a shift register, avoiding addition completely:

   shift_reg : std_logic_vector(7 downto 0) := "00001111";

   if rising_edge(clk) then
       output_signal <= shift_reg(7);
       shift_reg <= shift_reg(4 downto 0) & shift_reg(7 downto 5);
   end if;

You can do a little bit better than this using a DDR register to halve the phase noise on the output, but it is still very poor compared with using a PLL or MMCM.

[Saad Bin Shafique]

@hamster.. extremely nice demonstration

[Saad Bin Shafique]

On 12/5/2016 at 4:00 PM, D@n said:

If you don't mind the phase noise, you could take an 8-bit counter and add 3 to it on every clock, then use the most significant bit.

Dan

 

On 12/7/2016 at 1:15 PM, hamster said:

Dan meant a 'three bit' counter (that counts from zero to seven). when you adding 3 each cycle the counter will run as follows:

0, 3, 6, 1, 4, 7, 2, 5,  0, 3, 6, 1, 4, 7, 2, 5...

And the most significant bit of the counter will be:

0, 0, 1, 0, 1, 1, 0 ,1, 0, 0, 1, 0, 1, 1, 0 ,1...

That gives three 0-to-1 transitions every eight clock ticks, for  a total of 15,000,000 every second if you are using a 40MHz clock.

You can do the same thing with a shift register, avoiding addition completely:

   shift_reg : std_logic_vector(7 downto 0) := "00001111";

   if rising_edge(clk) then
       output_signal <= shift_reg(7);
       shift_reg <= shift_reg(4 downto 0) & shift_reg(7 downto 5);
   end if;

You can do a little bit better than this using a DDR register to halve the phase noise on the output, but it is still very poor compared with using a PLL or MMCM.

 

 

I want to ask you a simple question. How you figured out that a counter that counts 3 on each cycle, its MSB will generate 15MHz clock? Is there any technique by which we can tell this?

[hamster]

It's pretty simple, When adding 3 to a 3-bit counter, it will 'roll over' 3 times every 8 (or 2^3) cycles.  And 40 MHz * 3/8 = 15 MHz 

If it was a 5=bit counter it would roll over 3 times every 32 (2^5) cycles, so it would give 40MHz * 3/32 = 3.75 MHz