Jump to content
  • 0

XADC and the FFT


mohamed shffat

Question

Hello 

I'm trying to take an FFT on the FPGA after getting sampled data comes from XADC , but i couldn't get any results ! 

Here i figured out that the problem might be from the XADC's data , i tried to fix it but so far still no results . 

In my design i'm inserting an analog input signal to VP/VN pins on XADC header , then i'm trying to get some data comes out from the 1MSPS XADC . 

When i plot the output data it looks as it sampled correctly , but when i try to take its FFT whether on FPGA FFT CORE or on MATLAB , i get no results . The sampled signal and its FFT are shown below in the pics . 

Also i tried many frequencies for the input signal starts from 10KHz up to 480KHz , but they are all giving the same result , empty window in the Freq-domain . 

If someones know what's the problem i would really appreciate the help . 

Regards 

sampled sin with 50khz.jpg

Spectrum of the sampled sin.jpg

Link to comment
Share on other sites

Recommended Posts

12 hours ago, D@n said:

@mohamed shffat,

Congratulations, you've made a *lot* of progress since your last post!  From what you've shown above, I can't say that I know what the problem is, but I do know where to look.

May I assume that you are using pipeline mode?  If not, my comments below might need to be changed/adjusted.

Xilinx builds a pipeline mode for their FFT.  In this mode, the FFT can accept one sample on every clock cycle, and it can produce one sample on every output clock cycle.  There's a couple of gotcha's to using this technique, however--even though it's the one I would encourage you to use.  I'm also referencing the Xilinx's FFT IP Core, version 7.1.  If you are using another version of the core, you might notice some differences--probably mosty in signal names.

  1. It takes a couple of FFT's through the whole process before your first valid FFT will come out.  It's sort of a delay within the FFT.  I think the delay is about two and a half FFT samples, but ever after that delay it works.  Failing to wait for the full delay might be the cause of getting no data out.
  2. You need to set the START signal high for one clock on your first sample into the FFT.  Then afterwards, you'll want to check for DONE going high.  Failing to set the START signal might be a cause of getting nothing out.
  3. The core is designed to work with asynchronous designs in this fashion: samples from an A/D converter will rarely ever be at the same rate as the clock rate of the FFT.  To make certain you've got this right, set the CE line high *only* when you have a valid sample going into the FFT.  For example, if you are sampling your audio at 48kHz, but running the FFT at 80MHz, then you need to set the CE line so that it only goes high for only one clock roughly every 1666 clocks.  This signal also needs to gate your reading of the core's outputs.  Only read the outputs on those clock cycles where CE was high.  (Or is it on those cycles when DV is high?  The charts in the Xilinx doc's aren't clear ...)  Failure to properly account for the CE signal could explain some of the other problems you've been having in your other post.
  4. Many FFT's have a "RESET" line as well.  I don't see it in the instructions for this one, but failing to set it or worse failing to clear it might also result in the problems you are struggling with.

Many of these things *could* be your problem, but they aren't necessarily your problem.  You are going to need to dig a bit to be certain and know.

Let me know if this helps.  (or if you aren't using pipeline mode, and I therefore need to adjust my comments ...)  If not, we can dig deeper.  If it does help, I'd like to join you in a little victory dance.  :D

Dan

Thanks too much for everything MR. Dan , i really appreciate your helps .

My only problem that i wanted to explain on the post is that the output signals from the ADC can't be transformed to F-Domain using FFT , even on the MATLAB software ! Here i debugged the XADC individually and i took it's output , then i simulated the ADC's output signal and tried to take its FFT on MATLAB just to make sure that the signal is correct or not . But even the MATLAB gave me these results (Empty spectrum window with just to peaks in 0 point and the last point 1023 ) , so i'm wondering now why the sampled signal that i got from the XADC can't be taken by the FFT even on MATLAB ? Although it looks correct when i display it in T-Domain ? 

Greetings Sir :lol:

Link to comment
Share on other sites

@mohamed shffat,

Congratulations, you've made a *lot* of progress since your last post!  From what you've shown above, I can't say that I know what the problem is, but I do know where to look.

May I assume that you are using pipeline mode?  If not, my comments below might need to be changed/adjusted.

Xilinx builds a pipeline mode for their FFT.  In this mode, the FFT can accept one sample on every clock cycle, and it can produce one sample on every output clock cycle.  There's a couple of gotcha's to using this technique, however--even though it's the one I would encourage you to use.  I'm also referencing the Xilinx's FFT IP Core, version 7.1.  If you are using another version of the core, you might notice some differences--probably mosty in signal names.

  1. It takes a couple of FFT's through the whole process before your first valid FFT will come out.  It's sort of a delay within the FFT.  I think the delay is about two and a half FFT samples, but ever after that delay it works.  Failing to wait for the full delay might be the cause of getting no data out.
  2. You need to set the START signal high for one clock on your first sample into the FFT.  Then afterwards, you'll want to check for DONE going high.  Failing to set the START signal might be a cause of getting nothing out.
  3. The core is designed to work with asynchronous designs in this fashion: samples from an A/D converter will rarely ever be at the same rate as the clock rate of the FFT.  To make certain you've got this right, set the CE line high *only* when you have a valid sample going into the FFT.  For example, if you are sampling your audio at 48kHz, but running the FFT at 80MHz, then you need to set the CE line so that it only goes high for only one clock roughly every 1666 clocks.  This signal also needs to gate your reading of the core's outputs.  Only read the outputs on those clock cycles where CE was high.  (Or is it on those cycles when DV is high?  The charts in the Xilinx doc's aren't clear ...)  Failure to properly account for the CE signal could explain some of the other problems you've been having in your other post.
  4. Many FFT's have a "RESET" line as well.  I don't see it in the instructions for this one, but failing to set it or worse failing to clear it might also result in the problems you are struggling with.

Many of these things *could* be your problem, but they aren't necessarily your problem.  You are going to need to dig a bit to be certain and know.

Let me know if this helps.  (or if you aren't using pipeline mode, and I therefore need to adjust my comments ...)  If not, we can dig deeper.  If it does help, I'd like to join you in a little victory dance.  :D

Dan

Link to comment
Share on other sites

Archived

This topic is now archived and is closed to further replies.

×
×
  • Create New...