PmodOLEDrgb incorrect pin assignment Zedboard

[Loredana]

Hello,

My name is Cristina and I have a question regarding the connection of PmodOLEDrgb to Zedboard platform. I tried putting the PMOD on different connectors, but it only works on JB. I added the vivado-boards and vivado-library packages. 

I looked at the pin assignment from the Zedboard Hardware reference manual and noticed that, for instance, for JA1 and the PMOD the pins are differently mapped(Table 1). I tried to do the mapping like in the manual, but it still doesn't work.

PmodOLED pins	Zedboard Hardware Reference Manual	Vivado I/O Planning (put automatically when adding PmodOLEDrgb IP)
JA1	Y11	Y11
JA2	AA11	AA8
JA3	Y10	AA11
JA4	AA9	Y10
JA7	AB11	AA9
JA8	AB10	AB11
JA9	AB9	AB10
JA10	AA8	AB9

Any idea of what I'm doing wrong is more than welcome.

 

Best regards, 

Cristina

[D@n]

Hi Christina/ @Loredana!

Digilent often places differential signaling lines onto the JA port.  Vivado knowing that these lines are being used as differential signaling, may be tempted to match the lines together.  To keep that from happening, you need to make certain that the I/O standard for the pins is set to LVCMOS3V3.

Dan

[Loredana]

Hi,

I already set the I/O pins to LVCMOS3V3. 

So I have tested both the PmodOLEDrgb and PmodKYPD and they only work correctly on JB connector. 

The rest of the connectors (JA, JC and JD) do not work for PmodOLEDrgb at all and for PmodKYPD the application runs incorrectly (it doesn't display the correct digit/letter pressed).

Best regards,

Christina

[D@n]

@Loredana,

Ok, digging in a little bit more, I may have found the cause of your problem.  The ZedBoard XDC file has one of the pin maps you quoted/cited above, the board support file (XML) has another.  Further, the XDC file lists the pins out of order, making me wonder if someone didn't fat finger the pin declarations into your design in the wrong order.  You can find the problem in the "part0_pins.xml" file in the board support package.  Hopefully fixing that will fix things for you.

Dan

[jpeyron]

Hi @D@n and @Loredana,

Thank you D@N for catching this error. The board files were wrong. I have updated the board files on Github.  The PmodOLEDrgb and the PmodKYPD should now work on JA,JB,JC and JD.

thank you,

Jon

 

[Loredana]

Hello @jpeyron and @D@n,

I downloaded the new board files and now it works fine. 

Anyway, I figured out what were the issues and managed to get the OLEDrgb and Keypad working on PL PMods.

Now, I have a problem to get them working on the PS Pmod (JE).

I tried to use the the SPI1 controller, mapped on the MIO 10..15 pins (which i have read that are mapped on the JE1 Pmod), but it didn't work at all.

After that, I tried to use SPI0 mapped on the EMIO (in the design, I made it External) and tried to use constraints to map the SPI pins on the JE1 Pmod pins. Anyway, i wasn't able to do that because the JE1 pins are on the Bank500, so i can not select them.

I also tried to make the output of the Pmod Oledrgb module External and map these pins on the JE1 Pmod, but i had the same problem as using the SPI0.

Another idea was trying to write some physical constraints (to map the pins on JE1) directly in the OLEDrgb ip folder, but it didn't help. Vivado could not see the pins whici correspond to JE Pmod.

 

I'm quite new at hardware matters, so i'm sure that i'm missing something somewhere.

Anyway, any ideas would be appreciated.

Thank you both for helping! Have a nice day!

 

[sbobrowicz]

You will not be able to map pins from the PL to the Pmod JE pins, because they are connected to the so called "MIO" pins of the Zynq. These pin are only accessible from the PS I/O controllers (SPI0, SPI1, UART, etc.), not from anything in the PL. They can not be constrained in an XDC. See the diagram below. The MIO pins are represented by the blue "Processor I/O Mux" bar, and the pins connected the PL (including the Pmod JA-JD pins) are represented by the "Multi-Standard I/Os" blue bar. 

14 hours ago, Loredana said:

I tried to use the the SPI1 controller, mapped on the MIO 10..15 pins (which i have read that are mapped on the JE1 Pmod), but it didn't work at all.

This is the correct thing to do if you want to use JE pmod. I think the issue you are running into is that the SPI controller in the PS is not the same SPI controller that gets instantiated in the PmodOLEDRGB IP core. This means that the SDK software that you used with the PmodOLEDRGB will need to be ported to work with the SPI controller in the PS. You will also need to port the code that drives the other OLED control pins on the bottom row of the pmod to use the PS GPIO controller instead of the AXI GPIO controller (which is also included inside the PmodOLEDRGB).

Depending on your experience with Zynq and the baremetal Xilinx SDK libraries, the task I just described might end up being a long departure from whatever your final goal is. It may be better to just continue using the PmodOLEDRGB core and one of the PL pmods, and move on with your project. If you decide to keep going down the road of porting your software, we can help you along the way here :). 

Edit: For clarification here is what the Pmod connected MIO pins should be assigned to in the Zynq PS configure window of Vivado:

MIO0=GPIO
MIO9=GPIO
MIO10=SPI1 SDO (or MOSI, I don't remember what it is called in the GUI window)
MIO11=SPI1 SDI (or MISO)
MIO12=SPI1 SCLK
MIO13=SPI SS (or CS)
MIO14=GPIO
MIO15=GPIO

 

[Loredana]

Hello @sbobrowicz,

Thank you for replying!

I wanted to use the JE Pmod, connected to the PS because i wanted to use the RTCC Pmod from Digilent in my project. And I wanted to connect it on this port. 

Are there any sensitive differences in connecting the RTCC Pmod on the PL side or on the PS side? For example, i thought that if an error appears in the PL side, maybe i will still be able to read the time from the RTCC or something like this.

 

I see now why using the SPI1 controller is the only way to do this, but i'm not sure i understood what really means to port my code in the SDK or how to do it. Sorry for asking, but can you a little more specific?

Should I let the design as it is and try to do the matching between the SPI controllers in the SDK code?

 

PS. I tried to remake the design and activate SPI1 controller.

The thing that is unclear is what to do with the output pins of the Pmod OLEDrgp IP?

I tried to make the whole port External, but i obviously got an error which said that some of my ports are set to the "DEFAULT" value, instead of a user assigned specific value.

The second option was to let them unconnected and the bitstream is generated completely, but i got a critical warning which said that my input pins (when i expand the single output of the OLEDrgb Pmod, it contains several output pins and 8 input pins) are not connected to anything. 

 

Thank you in advance!

[sbobrowicz]

Quick question, are you planning on creating an embedded linux project (petalinux) or baremetal (Xilinx SDK)?

My advice might change depending on your answer to the above question, but chances are you don't stand to gain much using the PS pmod over the PL pmods. The tricky part is that the PmodOLEDRGB IP core you are using (from vivado-library) already contains an SPI controller inside of it, but it is not possible to route the SPI bus from the PL to the PS. This means if you want to use the PS Pmod, you will have to remove the PmodOLEDRGB IP core from your design and enable the SPI1 controller as described above. Since the demo SDK code you are using was designed to work with the PmodOLEDRGB IP core (which is really just a wrapper for a GPIO controller and SPI controller), you will need to write new code that works with the SPI1 controller and the PS GPIO instead. This is what I meant by port the demo code.

 

[Loredana]

Hello @sbobrowicz,

I am planning to create a baremetal application. 

I understood now what you meant by porting my demo code.

The thing is that I wanted to use the RTCC Pmod on the PS connector. This Pmod doesn't have an IP in the vivado-library which I downloaded from github.

I saw in a tutorial that you can use the Pmod Bridge (from the vivado library) if your Pmod IP doesn't already exist and customize it. 

Do you think that it is better to use the Bridge or to create my own IP for the RTCC? I'm thinking I should stop trying to connect the OLEDrgb on the PS Pmod and start trying to work directly with the RTCC.

Thanks!

 

[sbobrowicz]

Somebody designed the PmodRTCC IP core this summer, I was surprised to see that it is missing. I'm asking around now to find out where it is, and we will get it posted quickly (hopefully by the end of the day). Then you could simply drop in the PmodRTCC IP and use it with another PL pmod. Would that solve your problem?
 

[D@n]

There are also open source RTCC cores out there as well.

Dan

[jpeyron]

Hi Loredana,

I have updated and verified our github with the PmodRTCC IP. 

cheers,

Jon

[Loredana]

Thank you all for helping!

I will download it and try to do the design. I will connect it on the PL Pmod for now,  but for sure I'll try to make them work on the PS Pmod also.

 Loredana