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natsfr

Genesys 2 FMC trace length

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Hi Natsfr,

Here is the length for each GTX lane.

    DP0_C2M_N, Signal Layers Only, 88.4738mm

    DP0_C2M_P, Signal Layers Only, 88.4374mm

    DP0_M2C_N, Signal Layers Only, 85.3115mm

    DP0_M2C_P, Signal Layers Only, 85.2439mm

    DP1_C2M_N, Signal Layers Only, 83.6574mm

    DP1_C2M_P, Signal Layers Only, 83.6685mm

    DP1_M2C_N, Signal Layers Only, 84.467mm

    DP1_M2C_P, Signal Layers Only, 84.4307mm

    DP2_C2M_N, Signal Layers Only, 87.9247mm

    DP2_C2M_P, Signal Layers Only, 87.7015mm

    DP2_M2C_N, Signal Layers Only, 83.7533mm

    DP2_M2C_P, Signal Layers Only, 83.717mm

    DP3_C2M_N, Signal Layers Only, 88.5627mm

    DP3_C2M_P, Signal Layers Only, 88.5627mm

    DP3_M2C_N, Signal Layers Only, 88.0048mm

    DP3_M2C_P, Signal Layers Only, 87.8988mm

    DP4_C2M_N, Signal Layers Only, 85.605mm

    DP4_C2M_P, Signal Layers Only, 85.5874mm

    DP4_M2C_N, Signal Layers Only, 88.6059mm

    DP4_M2C_P, Signal Layers Only, 88.4302mm

    DP5_C2M_N, Signal Layers Only, 85.8485mm

    DP5_C2M_P, Signal Layers Only, 85.8844mm

    DP5_M2C_N, Signal Layers Only, 87.0384mm

    DP5_M2C_P, Signal Layers Only, 86.9516mm

    DP6_C2M_N, Signal Layers Only, 88.4989mm

    DP6_C2M_P, Signal Layers Only, 88.494mm

    DP6_M2C_N, Signal Layers Only, 85.889mm

    DP6_M2C_P, Signal Layers Only, 85.7132mm

    DP7_C2M_N, Signal Layers Only, 87.3225mm

    DP7_C2M_P, Signal Layers Only, 87.3225mm

    DP7_M2C_N, Signal Layers Only, 87.5185mm

    DP7_M2C_P, Signal Layers Only, 87.3185mm

    DP8_C2M_N, Signal Layers Only, 88.7324mm

    DP8_C2M_P, Signal Layers Only, 88.7324mm

    DP8_M2C_N, Signal Layers Only, 86.5751mm

    DP8_M2C_P, Signal Layers Only, 86.4853mm

    DP9_C2M_N, Signal Layers Only, 86.7981mm

    DP9_C2M_P, Signal Layers Only, 86.7981mm

    DP9_M2C_N, Signal Layers Only, 87.3832mm

    DP9_M2C_P, Signal Layers Only, 87.3832mm

 

and all of the pins on the FMC are differentially paired. 

 

cheers,

 

Jon

 

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Thanks for the answer.

Could you specify the length for each GTX lane ?

The generic IO/serdes are routed like differential pair ?

Thanks again for the answer.

PS: I think those kind of data should be in the doc (maybe I missed it ?), at least for "high end" board.

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