I'm a beginner to fpga programming and working on BASYS3. In my System Verilog code I have 2 2 bit outputs: la and lb. Assuming these are two traffic lights and 00 means red, 10 means yellow, 11 means green. If output is red, 3 leds will light. But I don't know how to implement it in constraint file. Normally, when an output is 1, I want to led to light and I write this kind of code:
But this time I want the led to light when output 0. Maybe I can write 2 more outputs that will become the opposite of my real outputs and I can use them in constraint but I wonder can I directly implement what I want in constraint file.
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aladinsane
I'm a beginner to fpga programming and working on BASYS3. In my System Verilog code I have 2 2 bit outputs: la and lb. Assuming these are two traffic lights and 00 means red, 10 means yellow, 11 means green. If output is red, 3 leds will light. But I don't know how to implement it in constraint file. Normally, when an output is 1, I want to led to light and I write this kind of code:
set_property PACKAGE_PIN U14 [get_ports {la[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {la[0]}]
But this time I want the led to light when output 0. Maybe I can write 2 more outputs that will become the opposite of my real outputs and I can use them in constraint but I wonder can I directly implement what I want in constraint file.
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