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Fouad Kiamilev

Need help with ZYBO HDMI project for class with 150 freshman undergrads

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Good afternoon,

We use digilent boards in our curriculum at University of Delaware electrical engineering department.

Next semester, we are upgrading our freshman digital design course from BASYS2 to ZYBO boards.

Our enrollment is typically 150 students.

We would like to add a project at the end of the semester that will be based on your HDMI example here:

https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-hdmi-demo/start

The idea is to give the student introduction to HDMI and let them make changes to the code you provide to do something cool with incoming video.

We have a group of students who are trying to do this as an exercise right before the class starts next semester.

They have run into trouble - they can't change the VHDL code that is generated by your example. The code generated is marked "read only". Even when they make changes outside of VIVADO, the system overwrites their changes.

My question to you is - can you share with us a method which can be used to add lines of code to your code examples.

 

Please let us know ASAP,

Fouad Kiamilev

Professor

ECE Department

UDEL

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Hey Fouad,

The reason some of the VHDL is read only is because they belong to one of Xilinx's IPs. You can use the IP packager to edit any of the Digilent owned cores.

Which IP block were you trying to edit? It makes sense to me to edit the dvi2rgb_0 core. You can do this by right clicking the core then select "edit in IP packager". You can then edit this VHDL and rebuild the IP.

Ill keep an eye here in case I misunderstood the question.

-Sam

 

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Hi Sam,

We followed your advice and edited the file rgb2vga_0 file in the packager. We were able to compile the code. The change we made was to hard code the output as shown below. We also uploaded a picture of the block diagram which indicates that the output of this module drives the VGA output. When we run the code we get a black screen instead of green one. Do you know what we may have gotten wrong?

 

Thanks,

Fouad

 

vga_pRed <= (others->'0'); --int_pData(VID_IN_DATA_WIDTH-1 downto VID_IN_DATA_WIDTH - kRedDepth);
vga_pBlue <= (others->'0'); -- int_pData(kBlueStart downto 1 + kBlueStart - kBlueDepth);
vga_pGreen <= (others->'1'); -- int_pData(kGreenStart downto 1 + kGreenStart - kGreenDepth); 
end Behavioral;

 

 

Screen Shot 2016-11-18 at 10.57.25 AM.png

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Hi Fouad,

I have not been able to get the vga to give anything other than black like you. One thing I saw is when using "others" i believe the syntax is  (others => '0');  instead of (others -> '0'); . After the thanksgiving break i will talk to the person that made the project to get an answer for this issue. 

cheers,

Jon

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Hi Fouad Kiamilev,

I personally haven't heard anything else either yet, but I will make sure your question is properly addressed.

Thank you for your patience,
JColvin

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JColvin -

Can you possibly elevate this question? We are purchasing 200X of your ZYBO boards for 3 classes next semester.

Two of those classes - I would like to include a project that does HDMI IN and VGA out.

You have a great code example but we are not able to make changes.

I have put a first question to this on November 11. It is now one month later.

Come on Digilent folks - we are spending $20K+ on your boards. And we are also introducing 200 students to your products.

I am happy to have technical support like this forum.

Waiting for 1 month for answer like what I am asking is not acceptable. 

The simple question we have is that digilent IP is protected so we are unable to modify it.

We are simply asking to get a version of your IP that we can change so that students can explore making their own image processing functions.

Are we asking for too much? I am upset that it is taking so long to answer our question.

Sorry for the rant. Hoping to hear from you soon.

Sincerely,

Fouad Kiamilev

Professor

ECE Department

University of Delaware

 

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Sorry for delay, your complaint is justified. We'll try our best to do better in the future. What you're describing is feasible and we should be able to figure it out with some quick back and forth. I'll keep this thread open at my workstation to try to get this resolved as quickly as possible.

I think the issue is that the the data signals need to be driven to zero during the blanking intervals. This was built into video timing specs in the olden days to account for how CRTs work, but for some reason modern LCDs still seem to freak out when you drive the color signals during blanking. The easiest way to fix this is to start with the original rgb2vga core and modify line 90 of rgb2vga.vhd to this:

int_pData <= "00000000" & "00000000" & "11111111"; --"red" & "blue" & "green"

Jon and I verified that this results in a green screen. I've attached the .vhd file that we used so the students can refer to it.

Please be aware that your students also need to run the Xilinx SDK software in order for the display to start working. This is because the video timing parameters and pixel clock all require some register configuration before they will begin generating the required sync signals. If your students are getting a "signal not detected" message (or similar) on their monitor, then this is likely the problem.

I can make myself available to have a call with you and/or your students in order to help them along a bit further. I'm not sure what their final goal is, but maybe we can make up some lost time. Private message me if you think it is worth while and we will set it up. 

--Sam Bobrowicz

rgb2vga.vhd

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Sam - we tried your suggestion. We made a fresh project and used the updated rgb2vga file. Synthesis Passed , Implementation Failed, Attached image was the error it gave me.

The 2nd image shows something we think has to do with failure to implement the code. We pressed "Upgrade IP" button but still failed implementation with same error.

Please advise.

Fouad

Screen Shot 2016-12-06 at 11.54.31 AM.png

Screen Shot 2016-12-06 at 11.55.21 AM.png

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Please advise what version of Vivado you are using.

You will need to reset all of the design runs found in the "design runs" tab. This can be done by right clicking them and selecting "Reset Run". Also please tell me how many design runs you see (this will let me know if you are doing an "Out of Context" build).

Also, it looks like you need to upgrade the rgb2vga IP core. This can be done from the tab you took an image of (2nd image) by clicking the "Upgrade Selected" button to upgrade the IP. This will make sure that your design uses the changes you have made to rgb2vga.vhd.

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We figured out the issue in a private message, seemed there was an unidentified issue with their vivado project. Taking and using our project seemed to solve their problem. The suggested changes to the rgb2vga core worked.

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