Serial To Parallel Conversion Testing

[1116345]

Hello Everyone,

I  actually wrote a code for serial to parallel conversion but when I am trying to test it, I am getting no results. I am using a light sensor as input  and then it passes  through an adc (in this case an arduino) and then the digital form of the input is fed to the FPGA which carries out the  serial to parallel conversion. At first i tried to synchronise the FPGA and the arduino by using same frequency but I could not reproduce 490Hz (arduino) for the FPGA. I am confused as to where there might be an error.

Codes for Serial to Parallel:

#

library IEEE;

use IEEE.STD_LOGIC_1164.all; 

use IEEE.STD_LOGIC_unsigned.all;

use IEEE.STD_LOGIC_arith.all;

 

 

entity serial is

port(

S1 : in STD_LOGIC;

clk : in STD_LOGIC;

x : in STD_LOGIC_VECTOR(0 downto 0);

P1 : out STD_LOGIC_VECTOR(7 downto 0)

    );

end serial;

 

 

architecture serial of serial is 

component Dff is

port

(

clk : in STD_LOGIC;

Din : in STD_LOGIC;

    Q : out STD_LOGIC

);

end component;

 

 

signal s: std_logic_vector (7 downto 0);

signal i: integer :=1; 

signal clk1 : std_logic;

begin

clk1 <= clk and x(0);

A0: Dff 

port map (

clk => clk1,

Din => S1,

Q => s(0)

);

 

M1 :

for i in 1 to 7 generate

Ai: Dff 

port map (

clk => clk1,

Din => s(i-1), 

Q => s(i)

);

 

P1 <= s;

 

end generate M1;

 

 

 

end serial;

 

#

 

 

 

codes for Dff:

#

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_unsigned.all;

use IEEE.STD_LOGIC_arith.all;

 

entity Dff is

port(

clk : in STD_LOGIC;

Din : in STD_LOGIC;

Q : out STD_LOGIC

 

    );

end Dff;

 

 

architecture Dff of Dff is

begin

process  (clk ,Din)

begin

if (rising_edge (clk)) then

Q <= Din;

 

end if ;

end process;

 

end Dff;

#

 

 

codes for debounce:

#

library IEEE;

use IEEE.STD_LOGIC_1164.all;

 

entity debounce is

port(

input : in STD_LOGIC;

cclk : in STD_LOGIC;

clr : in STD_LOGIC_VECTOR (0 downto 0);

output : out STD_LOGIC

    );

end debounce;

 

 

architecture debounce of debounce is  

signal d1, d2, d3: STD_LOGIC;

begin

process (cclk, clr(0))

begin

if clr(0) = '1' then 

d1 <= '0';

d2 <= '0';

d3 <= '0';

elsif cclk'event and cclk = '1' then 

d1 <= input;

d2 <= d1;

d3 <= d2;

end if;

end process;

output <= d1 and d2 and not d3;

 

 

 

 

end debounce;

 

codes for clkdiv :

 

#

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_unsigned.all;

use IEEE.STD_LOGIC_arith.all;

 

 

entity clkdiv is

port(

      mclk  : in  STD_LOGIC;

      clr : in STD_LOGIC_VECTOR(0 downto 0);

           clk : out STD_LOGIC_VECTOR (2 downto 0);

  clk47: out STD_LOGIC;

           clk381:out STD_LOGIC

    );

end clkdiv;

 

 

architecture clkdiv of clkdiv is  

signal q: STD_LOGIC_VECTOR (23 downto 0); 

 

begin

 

     

   process (mclk ,clr(0))

   begin 

    if clr(0)= '1' then 

  q <= X"000000" ;

  elsif mclk 'event and mclk  = '1' then 

  q <= q + 1;

  end if ;

     end process;

clk(0)<= q(0);

clk(1)<= q(1);

clk(2)<= q(18);

        clk381<= q(17);

clk47<= q(20);

 

end clkdiv;

##

 

codes for top level

##

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_unsigned.all;

use IEEE.STD_LOGIC_arith.all;

 

 

entity serial_top is

port(

    JB1 : in STD_LOGIC;

    sw : in STD_LOGIC_VECTOR(1 downto 0);

clk : in STD_LOGIC;

led : out STD_LOGIC_VECTOR(7 downto 0)

    );

end serial_top;

 

 

 

architecture serial_top of serial_top is 

component clkdiv

port(

mclk : in STD_LOGIC;

clr : in STD_LOGIC_VECTOR(0 downto 0);

clk : out STD_LOGIC_VECTOR(2 downto 0);

clk47 : out STD_LOGIC;

clk381 : out STD_LOGIC);

end component;

for all: clkdiv use entity work.clkdiv(clkdiv);

 

 

component serial

port(

S1 : in STD_LOGIC;

clk : in STD_LOGIC;

x : in STD_LOGIC_VECTOR(0 downto 0);

P1 : out STD_LOGIC_VECTOR(7 downto 0));

end component;

for all: serial use entity work.serial(serial);

 

component debounce

port(

input : in STD_LOGIC;

cclk : in STD_LOGIC;

clr : in STD_LOGIC_VECTOR (0 downto 0);

output : out STD_LOGIC);

end component;

for all: debounce use entity work.debounce(debounce);

 

 

signal clk381: STD_LOGIC;

 

signal output: STD_LOGIC;

begin

Label1 : serial

port map(

S1 => output,

clk => clk381,

x(0) => sw(1),

P1 => led

); 

 

Label2 : clkdiv

port map(

mclk => clk,

clr(0) => sw(0),

clk381 => clk381); 

 

Label3 : debounce

port map(

input => JB1,

cclk =>  clk381,

clr(0) => sw(0),

output => output

);

 

end serial_top;

####

 

[cristian.ignat]

Hi,

 

You can generate 49 MHz clock frequency using DCM/PLL and you can divide this frequency to obtain 490Hz. 

Other solution will be to use a pin from the Arduino which generates the 490Hz clock and on FPGA you should use your FPGA board frequency like clock and 490Hz from Arduino like a clock enable. Your code should be something like this:

 

signal clk490Hz_1: std_logic:='0'; --this will be the previous value of clk490Hz (is delayed with a clock period)

 

--......................................

 

process(clk)

begin

 if clk'event and clk = '1' then

  clk490Hz_1 <= clk490Hz;

 end if;

end process;

 

process(clk)

begin

 if clk'event and clk = '1' then

  if clk490Hz = '1' and clk490_1 = '0' then

   -- your synchronization code

  end if;

 end if;

end process;

 

 

We can help you more if you tell us what means that serial communication. There are many serial protocols and we don't know exactly what do you want to do. A signal diagram can help us.

 

Best Regards,

Cristian