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ireon

Partial Reconfiguration using ICAP and AXI DMA

Question

Hello I'm using a ZYNQ Zedboard development board. I'm studying the Partial Reconfiguration using ICAP. I implemented a system with Zynq Processing Unit, ICAP and AXI DMA. The DMA accesses to the memory and transfers the partial bitstream from DDR3 to ICAP using 32 bit AXI stream. Using a Clock Wizard peripheral I examined the frequency behavior of the system and I got that the transfer time from ICAP to reconfigurable partition decreases linearly up to 200 MHz, beyond this frequency there is a saturation and the time doesn't decrease with increasing frequency. I found on the AXI DMA datasheet that maximum frequency using AXI stream for ZYNQ device is 200 MHz. My question is how does the DMA receiving a clock input greater than 200 MHz to work anyway to 200 MHz? DMA uses an interna FIFO and performs an input clock domain control?

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The default ICAP works to 100MHz, but it's possible to increase this frequency by overclocking. In fact in my system the transfer time from ICAP to reconfigurable partition decreases linearly up to 200 MHz. Beyond this frequency I can't rise, so I supposed this as saturation frequency. Then the limit seems to be the DMA and I would know how it works overclocking over the max frequency, so as to explore ways to overcome the limitation.

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Indeed I think that overlocking isn't a supported feature, anyway by overlocking I manage to improve the perfomances. My study is about the limit using this system with overclocking and this limit seems to be 200 MHz . I'm trying to know how Xilinx AXI DMA works and I suppose that AXI DMA uses an internal FIFO to limit the clock frequency, but I'm not sure about that and in the Xilinx documentation I I found nothing.

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Hi ireon,

Unfortunately we would not have more information about the AXI DMA. I would suggest to contact Xilinx about the AXI DMA.

cheers,

Jon

Edited by jpeyron

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