Myself trying to make Ethernet link up (without lwip) on Genesys Virtex5 Board. I generated EMAC0 wrapper with loop back from Xilinx Code Generator , modified ucf for board schematic.
Reeceive link is working fine , i.e my board is able to receive I Gbps packets from PC and in chipscope pro , I could see packets loop backed on the TXD lines and PHY TX led is blinking but no packet is reaching PC .
The problem , I assume may be the TXD line delays and PHY not getting proper data from FPGA . I don't have visibility to the TXD lines at PHY side . I tried out a couple of things thinking that the PHY may not be getting window to sample data properly.
1) GTXCLK is shifted at 90,180,260 PHASES using DCM ..No luck :-(
2) Drive strength of I/O reduced which can reduce EMI interference
3) Slew rate changed
Nothing worked out ..So please help me out with some suggestions.
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supriyauk
Hi ,
Myself trying to make Ethernet link up (without lwip) on Genesys Virtex5 Board. I generated EMAC0 wrapper with loop back from Xilinx Code Generator , modified ucf for board schematic.
Reeceive link is working fine , i.e my board is able to receive I Gbps packets from PC and in chipscope pro , I could see packets loop backed on the TXD lines and PHY TX led is blinking but no packet is reaching PC .
The problem , I assume may be the TXD line delays and PHY not getting proper data from FPGA . I don't have visibility to the TXD lines at PHY side . I tried out a couple of things thinking that the PHY may not be getting window to sample data properly.
1) GTXCLK is shifted at 90,180,260 PHASES using DCM ..No luck :-(
2) Drive strength of I/O reduced which can reduce EMI interference
3) Slew rate changed
Nothing worked out ..So please help me out with some suggestions.
Thanks & Regards,
Supriya
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