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dkinman

Program Zybo board QSPI FLASH with .mcs file

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In the past, I have been able to program the QSPI flash of a Nexys4DDR board with a .mcs file that was generated from the .bit file. I am now using a ZYBO board and when I follow the same procedure, it seems I can program the flash, but after a power cycle the FPGA program does not load and execute as expected. Keep in mind I want to use the only the PL in this case.

Has anyone done this with success?

 

Edited by dkinman

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Unfortunately for pure PL designs on the zybo, you are still required to run an SDK project to program it. The QSPI is hardlined to the arm core so you will have to create a boot.image like the process shown here https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start but you just wont have an SDK project to include. You will only need the fsbl and the bin file.

-Sam

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Hello,

I followed the instructions as best as possible since I am using a Zync and the instructions are for a Microblaze boot (SREC_SPI_BOOTLOADER). None the less, it did not work using the ZYNQ_FSBL boot loader and offset 0x00300000. Also, I have the programming jumper on the middle 2 pins.

Can you write a simple RTL program to turn on a led and modify the procedure to create the bit file and create the fsbl boot image while targeting a Zybo board?

P.S. I can program the FPGA using the bit file from SDK. I can program the FLASH successfully, but it will not boot from FLASH after POR.

Thanks,

David

 

 

 

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Hey David,

So just successfully did this implementing a clock divider driving an LED.  I didn't realize the Zybo's SDK programming guide is not correct. Ill be updating it soon to match the Zedboards guide here. Ill quickly explain my steps below though since I don't know how fast Ill be able to fix it.

1. create a base zynq design and verify. (create block diagram, add zynq core, run block automation, connect FCLK_CLK0 to M_AXI_GP0_ACLK)

2. generate the top wrapper from the block design and don't let vivado auto update the wrapper. 

4. edit the top file to include your HDL module

5. generate bitstream

6. file -> export -> hardware (include bitstream)

7. open sdk

8. file-> new -> application project

9. select FSBL and create project

10.  Xilinx tools-> create boot image

11. choose file output location

12. add file -> <FSBL>.debug/<FSBL>.elf'

13. add file ->  hardware platform/.bit

14. click ok

15. xilinx tools -> program flash and choose your exported .bin file

16. switch jumper to qspi and reset board

 

I'm pretty sure that is the rough procedure I used to get this working if it still doesn't work stay tuned for the new guide. Ill also include my small proof project.

 

-Sam

zybo_PL_flash.zip

Edited by sLowe

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On 10/13/2016 at 6:30 AM, sLowe said:

Unfortunately for pure PL designs on the zybo, you are still required to run an SDK project to program it. The QSPI is hardlined to the arm core so you will have to create a boot.image like the process shown here https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start but you just wont have an SDK project to include. You will only need the fsbl and the bin file.

-Sam

Hai .,
i had bought DIGILENT Zybo Kit 7000 series Family.
i had flashed the Zynq boot image with the following offset values successfully on Zynq Board via Xilinx SDK (ver: 2016.4)
                     fsbl.elf
                     system_wrapper.bit
                     U-boot.elf
                     U-image 0x600000
                     dtb file 0xA00000
                     ramdisk 0xA20000
 
But the FPGA done_led is not working automatically after a power cycle.
 
on the other hand, if i program the FPGA MANUALLY via Xilinx SDK , it works and kernel image loads successfully from QSPI Flash.
 
How to Make FPGA done_LED works automatically?
Thanks in Advance...

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Hey Diya,

Sorry if this is late, but it sounds like your jumper is not in the correct position? In section 3.2 of the Reference Manual  here, it shows you what to set it as. The manual also references a project that can take you through the process. That can be downloaded on the resource center page or here. base system design

-Sam

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