How to define on board files an AXI QUAD SPI controller with 2 slaves

[a.gamez]

Hi

 

I'm writing a new board file based on the board.xml from the ARTY but with a modified SPI device.

I want to use another pin as SS2 (select slave, or chip select, 2), in order to communicate with two SPI devices through the same bus.

This is the diff between original board files and mine:

 

--- a/new/board_files/newboard/1.0/preset.xml
+++ b/new/board_files/newboard/1.0/preset.xml
@@ -25,6 +25,7 @@
                        <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
                        <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
                        <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+                       <user_parameter name="CONFIG.C_NUM_SS_BITS" value="2"/>
                </user_parameters>
        </ip>
   </ip_preset>

--- a/new/board_files/newboard/1.0/board.xml
+++ b/new/board_files/newboard/1.0/board.xml
@@ -579,19 +579,22 @@
               <pin_map port_index="0" component_pin="spi_sclk_i"/> 
             </pin_maps>
           </port_map>
-          <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
+          <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in" left="1" right="0">
             <pin_maps>
-              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+              <pin_map port_index="0" component_pin="spi_ss_i_0"/> 
+              <pin_map port_index="1" component_pin="spi_ss_i_1"/> 
             </pin_maps>
           </port_map>
-          <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
+          <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out" left="1" right="0">
             <pin_maps>
-              <pin_map port_index="0" component_pin="spi_ss_i"/> 
+              <pin_map port_index="0" component_pin="spi_ss_i_0"/> 
+              <pin_map port_index="1" component_pin="spi_ss_i_1"/> 
             </pin_maps>
           </port_map>
           <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
             <pin_maps>
               <pin_map port_index="0" component_pin="spi_ss_i"/> 
             </pin_maps>
           </port_map>
         </port_maps>

 

I haven't added another pin_map inside SS_T, as AXI QUAD SPI when configured with two slave devices, still only provides a single SS_T pin:

 

 

Finally, I've replaced original spi_ss_i on part0_pins.xml with two lines, one defining loc pin of spi_ss_i_0 and one for spi_ss_i_1 (never mind exact pin numbering):

 

- <pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="B20"/>
+ <pin index="93" name ="spi_ss_i_0" iostandard="LVCMOS33" loc="B20"/>
+ <pin index="94" name ="spi_ss_i_1" iostandard="LVCMOS33" loc="C20"/>

 

However, Vivado won't let me use this board definitions with the following message:

 

WARNING: [Board 49-69] Validation failed for board file vivado-boards/new/board_files/newboard/1.0/board.xml:
 Pin Map file does not provide LOC constraints for spi_ss_iCOMP : agamez:newboard:part0:1.0

What should I do?

 

[AndrewHolzer]

Hello a.gamez,

We've run into issues similar to yours, but we haven't encountered your issue specifically. Whenever we've run into something like this, we've just had to find ways to work around it. If I had to guess, there is something behind the scenes that needs to happen for the AXI QUAD SPI IP core to increment the SS_T pin count. Unfortunately, the core is Xilinx IP and we don't have the means to check the source and make changes.

I would bring this to Xilinx's attention to see what they have to say on the matter. They may respond saying this is a shortcoming of the board files system, or that it is something to do with the IP core itself. In any case, they may provide more insight than we can.

Still, if you have any further issues or questions, we'd be more than happy to work with you.
AndrewHolzer