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Wilton

Zybo Block interface

Question

I'm still trying to connect the dots between the various pieces of Vivado.  I just created an xdc file for a project.  It has some differential I/O.  By looking at examples, I figured out that PACKAGE_PIN is not needed for the _N pin.

Next is how I connect a block IP to this.  I've done it for some simple single ended uses.  But here are two differential examples I can't sort out:

1.  Create a differential clock.  The block diagram has FCLK_CLK1 which I have set to 40 MHz.  The xdc file has:

#8 channel 40 Ms/s DDR Serial ADC
#IO_L4P_TO_34
set_property PACKAGE_PIN V12 [get_ports ADCCLKout_p]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports ADCCLKout_p]
#IO_L4N_T0_34  pin W13
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports ADCCLKout_n]
 
How do I connect the two together?  I put an external port on FCLK_CLK1 and named it ADCCLKout.  Or should that bt ADCCLKout_p?  or?  or do I have to place an OBUFDS between the two?  If so can that be done at the block level or does it have to get buried in a Verilog file somewhere?
 
2.  I instantiated an XADC Wizard with four ADC inputs.  In this case I created xdc file entries for each:
#The following pins are external ADC inputs.
#The IOStandard does not matter so long as it is compatible with the I/O Bank voltage
#IO_L5P_TO_AD9P_35
set_property PACKAGE_PIN E18 [get_ports ADC_INT_3V3IN_p]
set_property IOSTANDARD LVCMOS33 [get_ports ADC_INT_3V3IN_p]
#IO_L5N_TO_AD9P_35
set_property PACKAGE_PIN E19 [get_ports ADC3V3IN_n]
set_property IOSTANDARD LVCMOS33 [get_ports ADC3V3IN_n]
 
Again, the question is how to tie this to the block?  I put an external port on Vaux6, for example and named it . . .  Well I named it ADC_INT_3V3IN, but maybe I needed the _p.  But then they aren't defined as differential in this case, so it couldn't find the _N.
 
Help me bridge this gap.  I haven't been able to find anything on-line or in UGs.
Thanks
 

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I have at least a partial answer.  By looking at the "External Interfaces" and expanding ADC_INT_3v3IN I found out the program breaks that down into two signals suffixed with "_v_n".  Making the xdc file conform to that solved the ADC issue.  (At least it built without error, I haven't tried to use it in SDK, yet.)

And while this is a bit more crude than I would have hoped for, I found "Utility Buffer" in the IP that can be configured to be a OBUFDS which I could then map to external ports that matched the xdc file.  I'd have preferred to be able to tell it the port was differential and have it infer the OBUFDS because it would keep the block diagram much simpler, but this did the trick.

 

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Hi Wilton,

For question 

1) Using IP's in the block design you would use the util_ds_buf to set up a differential pair. You would not be able to use DIFF_HSTL_I_18 because our pmod pins are set to 3.3 and are not adjustable. If you are able to use 3.3 then TMDS is the setting in the constraint file. If you are wanting to use the block design to do this i have included a screen shot below and all you would need to do is constrain the external pins in the xdc.

2) You would need to use the _p.  Going off of you example of  Vaux6 per the schematic for AD6P and AD6N you would need to use pin K14 and pin J14. So it would look lik this in the constraint file.

set_property PACKAGE_PIN K14 [get_ports ADC_INT_3V3IN_p]

set_property IOSTANDARD LVCMOS33 [get_ports ADC_INT_3V3IN_p]

set_property PACKAGE_PIN J14 [get_ports ADC_INT_3V3IN_n]

set_property IOSTANDARD LVCMOS33 [get_ports ADC_INT_3V3IN_n]

Once you have created the wrapper you will need to match up the name in the wrapper to what they are named in the XDC so it probably wont be ADC_INT_3V3IN_p and ADC_INT_3V3IN_n.

 

thank you,

Jon

 

diff_pair.jpg

Edited by jpeyron

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