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Nexys4-ddr Resource Center Updates?

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Hi,

some news about Nexys4-DDR Resource Center updates?

 

​I bought the board and I'm interested in sections:

Embedded Linux Materials

- Advanced Microblaze Design with MIG, Ethernet, UART & GPIO

Constraint Files

- Xilinx Memory Interface Generator (MIG) Project

- XADC Demo

Edited by KaitlynFranz

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The XADC demo just went live. 

 

The constraint files and MIG project should already be posted, that is an oversight. I will try to get this fixed in the next day or so.

 

Advanced Microblaze design is still being worked on, I'm hoping it will pop out pretty soon.

 

Last, the embedded linux materials are still a ways out. Currenlty ZYBO linux materials are being worked on, and these are in line ahead of the Nexys4-DDR. When you see the ZYBO Getting started with embedded Linux guide go up on ZYBO resource center, you can be sure the Nexys4-DDR guide is not far behind it.

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Hi,

 

I found that NEXYS4 DDR reference manual in the ETHERNET PHY section mentions: 

"An EDK demonstration project that properly uses the Ethernet PHY can be found on the Nexys4 DDR product page at www.digilentinc.com"

Any plans to upload it soon?

Just bought the board and looking forward to use ETHERNET PHY asap.

Thanks!

Alex Shrabstein

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Hi,

 

The Ethernet PHY demo is getting close to completed once some timing constraints are ironed out to help keep the demo solid.  The advanced microblaze design that Sam mentioned is also getting worked on; however, the person working on it has limited time to work on due to finals week approaching at the local university. 

 

We'll let you know when those are completed and available.

 

Thank you for your patience,

JColvin

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Hi,

 

Here is a link to a "beta" version of the project at this dropbox link.  From what I understand, it is a working project that just needs a little more work in terms of explanations about timing constraints.  There are also some notes about the project that I was told to pass on:

 

 

Notes about the project

- The oddr_phy_clk_0 component is a simple ODDR instantiation in order to p[rovide the 50MHZ reference clock to the Ethernet PHY (phy_clk). The IP should be in the local repository. If not you can repack it, the source file can be found in the unpacked_project_dirNexys4_DDR_Vivado_Ethernet_2014_4Nexys4_DDR_Vivado_Ethernet_2014_4.srcssources_1ipsharednatinst.comoddr_phy_clk_v1_05930728aoddr_phy_clk.vhd
 
- The outgoing reference phy_clk is shifted to -22.5 degrees versus the reference clock of the mii_to_rmii component. Although even with a zero phase shift the project works, we found out on the oscilloscope that the RMII timings are better with a -22.5 degrees phase shift.
 
- Regarding input - output timing constraints for the RMII interface, please check the constraints in the Nexys4DDR_Master.xdc file, lines 259-280 (at the end of the file). You should use these constraints. Commented constraint lines can be removed. Is to be follow an explanation about the input - output constraint values
 
About the software applications:
 
IMPORTANT:
 
We found a bug in the lwip library that prevents the  SMSC LAN8720A PHY to work correctly.
 
This is because the get_IEEE_phy_speed_emaclite(XEmacLite *xemaclitep) function in the xemacliteif.c writes to the PHY advertisment register (address 5), but also changes the IEEE selector field, look in to the SMSC LAN8720A datasheet, page 54, the Auto Negotiation Link Partner Capability Register.
 
This seems to be a bug from Xilinx, the code is making a write to the register instead of a read-modify - write operation; we'll open a webcase for this.
 
The easiest workaround, without needing to change the xemacliteif.c file: on the Board Support Package Settings, set the 140 options, temac_adapter_options, phy_link_speed to CONFIG_LINKSPEED100. In this case at the compile and run time a different function will be called to set the PHY speed.

 

Thanks,

JColvin

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