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takieddine

Buffering Video feeds in HDMI, Atlys board

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Hi everybody,

Could someone please give a brief explanation how the DDR2 in the Atlys demo projects work for video buffering at a resolution of 1600 x1200 30 fps, I got confused in the VHDL code ?

Thank you,

TK SAIDI

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Hi  TK SAIDI,

Which demo are you refering to? Is it the EDK HDMI Demo? If that is the case you can look at the documentation for the MPMC (i believe) here to have a better understanding of how we interacted with the MPMC with the HDMI_in and HDMI_out. You can also look at the HDMI_in to see how we made our custom IP core. In the zipped demo it comes with a pdf that has a basic fpga logic diagram in it as well. Hope this helps! 

thank you,

Jon

 

Edited by jpeyron

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Hi jperyon,

I am refereing to the ISE project that configures VmodCam at 1600x1200 @ 30 fps, I would like to know how I can change the resolution 

I tried to change the display to be 1280x720, and I have no idea of how to control the fp, I made the following modification in the VHDL code

IRD & x"30001580", -- Chip version. Default 0x1580

		IWR & x"33860501", -- MCU Reset
		IWR & x"33860500", -- MCU Release from reset
		
		IWR & x"32140D85", -- Slew rate control, PCLK 5, D 5

		IWR & x"341E8F0B", -- PLL control; bypassed, powered down
		IWR & x"341C0250", -- PLL dividers; M=80,N=2,fMCLK=fCLKIN*M/(N+1)/8=80MHz
		IWR & x"341E8F09", -- PLL control; Power-up PLL; wait 1ms after this!
		IWR & x"341E8F08", -- PLL control; Turn off bypass
		
		IWR & x"32020008", -- Standby control; Wake up

		IWR & x"338C2797", -- Output format; Context B shadow
		IWR & x"33900030", -- RGB with BT656 codes
		IWR & x"338C272F", -- Sensor Row Start Context B
		IWR & x"33900004", -- 4
		IWR & x"338C2733", -- Sensor Row End Context B
		IWR & x"339002DB", -- 1211, 731 => 2DB  Modified
		IWR & x"338C2731", -- Sensor Column Start Context B
		IWR & x"33900004", -- 4
		IWR & x"338C2735", -- Sensor Column End Context B
		IWR & x"3390064B", -- 1611, 1291 => 50B  modified
		IWR & x"338C2707", -- Output width; Context B
		IWR & x"33900500", -- 1600, 500 => 1280  modified
		IWR & x"338C2709", -- Output height; Context B
		IWR & x"339002D0", -- 1200,720=> 2D0 Modified
		IWR & x"338C275F", -- Crop X0; Context B
		IWR & x"33900000", -- 0
		IWR & x"338C2763", -- Crop Y0; Context B
		IWR & x"33900000", -- 0
		IWR & x"338C2761", -- Crop X1; Context B
		IWR & x"33900500", -- 1600, 1280 => 500  Modified
		IWR & x"338C2765", -- Crop Y1; Context B
		IWR & x"339002D0", -- 1200, 720=> 2D0 Modified 
      IWR & x"338C2741", -- Sensor_Fine_IT_min B
		IWR & x"33900169", -- 361 		

		IWR & x"338CA120", -- Capture mode options
		IWR & x"339000F2", -- Turn on AWB, AE, HG, Video
		
		IWR & x"338CA103", -- Refresh Sequencer Mode
		IWR & x"33900002", -- Capture
		IRD & x"33900000", -- Read until sequencer in mode 0 (run)
		
		IWR & x"301A02CC" -- reset/output control; parallel enable, drive pins, start streaming

For the video timing controller I modified the input resolution as follows

Inst_VideoTimingCtl: entity digilent.VideoTimingCtl PORT MAP (
		PCLK_I => PClk,
		RSEL_I => R1280_720P, --this project supports only 1280x720
		RST_I => VtcRst,
		VDE_O => VtcVde,
		HS_O => VtcHs,
		VS_O => VtcVs,
		HCNT_O => VtcHCnt,
		VCNT_O => VtcVCnt
	);

Finally I modified the addresses in the FBCTL as follows

WRADDRCNT_PROC_A: process (CLKA)
   begin
      if Rising_Edge(CLKA) then
			if (pa_int_rst = '1' and p1_wr_empty = '1') then
				pa_wr_addr <= 0;
         elsif (stateWrA = stWrCmd) then
				if (pa_wr_addr = 1280*720*2/(WR_BATCH*4)-1) then
					pa_wr_addr <= 0;
				else
					pa_wr_addr <= pa_wr_addr + 1;
				end if;
         end if;        
      end if;
   end process;
                                           
  WRADDRCNT_PROC_B: process (CLKB)
   begin
      if Rising_Edge(CLKB) then
			if (pb_int_rst = '1' and p2_wr_empty = '1') then
				pb_wr_addr <= 0;
         elsif (stateWrB = stWrCmd) then
				if (pb_wr_addr = 1280*720*2/(WR_BATCH*4)-1) then
					pb_wr_addr <= 0;
				else
					pb_wr_addr <= pb_wr_addr + 1;
				end if;
         end if;        
      end if;
   end process;

Can you please tell me why I get no video feeds when Implementing the system and downloading the bit file to the FPGA, ? also I would like to use the video timing controller and HDMI controller with BRAM to display the video feeds at a resolution of 640x480, how can I do that ?

please you will provide me a great help if you guide me to solve this problem

Thank you very much,

TK SAIDI

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Hi TK SAIDI,

Thank you for the clarification of which project. There is not enough BRAM to use in the VmodCAM designs so you will need to use the MIG. I would suggest to use the VmodCAM_Ref_HD_Demo_13 and scale down to 1280 x 720 if you are not wanting to use the 1600 x 900. You could also use the VmodCAM_Ref_VGA_Demo_13 at 640 x 480. Unfortunately the Image sensor is very complicated and we were only able to get the two resolutions.

thank you,

Jon

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Hi Jon,

Thank you for being helpful, I am willing to use the demo design for video processing, according to the demo I think that I can store N number of rows, process them and then store the next, N rows, redo the processing, and keep rpeating the process until the whole frame is read, like that I believe that the BRAM will be more than enough.

So I am willing to use VGA resolution at grayscale level, can you please guide as how to scale down the image from 1600x900 to 640x480, the VGA demo splits the screen to two views, I need to configure it for one view, please I am working on a stereo vision project and I am stuck at the display problem your help will be surely appreciated

Thank you,

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Can you please explain how to configure sensor row start and end context B, also can you please tell me the practical difference between context A and B ?

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Hi TK SAIDI,

If you can make your project work with either 1600 x 900 or 640 x 480 it would save alot of development time. The process to scale down to a lower resolution with a video stream is a complex task called bilinear scaling. Googling bilinear scaling i found this here. I believe all you need is to register. Once registered you can download the ip's and they do not have a cost associated with them. This ip was developed for the Altera Cyclone III 3C120 so I'm not sure how compatible it will be but it can give you a starting point for the process.

thank you,

Jon

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Thank you Jon,

Maybe you did not understand me, could I modify the configuration of the camera in the project (1600x900) in order to use VGA resolution(640x480), I am sorry beacause I am new in this field so that what I meant by scaling down the resolution, is modfiying the configuration enough to change the resolution and displaying the video feeds at the new resolution, and also I have another question what is row start and end sensor, and how it is related to the selected resolution and context ?

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Hi Hi TK SAIDI,

 Unfortunately, we were only able to get the VmodCAM to work in the 2 resolutions with the 2 different designs. You can get more information about the MT9D112 from here with a partial reference manual of the MT9D112. For more information about the MT9D112 I would suggest to request Micron for the full data sheet. 

thank you,

Jon

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Hi Jon,

Are you saying that the VmodCam cannot work with a resolution between 1600x900 and 640x480 ? my problem is that I couldn't display the video feeds on an HD tv screen after I changed the resolution from 1600x900 to 640x480n despite the fact that the vga demo project works just fine, hence I would like to understand the difference between context A(preview mode) and context B (capture mode), I am waiting for your response.

Thank you,

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