Expanding BRAM for a Microblaze application

[shubhamgandhi]

I'm working with a Kintex-7 board. Currently my application relies on external DDR, but I want to turn it entirely off internal memory on the FPGA. From what I have gathered online, this is possible to do, but haven't been able to find a clear answer on how to do this with the modern SDK.

I can change my linker script to allocate more memory to BRAM and the program will compile. But I"m having trouble in Vivado when trying to generate required hardware with enough memory. I have Microblaze with the following ports:

 

DLMB (data mem) <---> LMB  <----> LMB BRAM Controller1 <---> Block memory gen 1

ILMB (instr mem) <-----> LMB <----> LMB BRAM Controller2 <---> Block memory gen 1

AXI_DC (data cache) <-----> External DDR

AXI_IC (instr cache) <------> External DDR

 

I want get rid of the external DDR from the design, but the program is too large to sit in the default BRAM allocated size of 32k x 32b wide. Seems like this is hard limit for one block, but it is possible to cascade more to expand the depth. I have verified that there is way more than enough total BRAM in the FPGA to store the program.

In Vivado, 

Has anyone be able to do this or knows how it can be done?

[sLowe]

You should be able to instantiate additional BRAM by placing a BRAM controller IP in your block design. When you run block and connection automation, you should be able to use this block memory for your program.  Just make sure it gets connected through a memory interconnect.

 

[shubhamgandhi]

I tried that (see below), with the new added blocks circled in red. First problem I run into here is: where do I connect the LMB block? The tooltip says "No matching connections found for LMB_M interface". 

 

Second problem is that the new BRAM block is locked to 8k x 32bit, just like the other one (see below). I need total BRAM of about 100 times this size. 

[sLowe]

This looks like a serious limitation of the BRAM controller IP in Vivado. The best answer I could find to this problem was found on this thread.

https://forums.xilinx.com/t5/Embedded-Development-Tools/AXI-BRAM-controller-Unable-to-change-address-to-Least/td-p/553451

Basically they generate a wrapper for the block design after making the axi bus external. Then manually attach a generic BRAM IP to the bus in a top file above the block design. I haven't tried it but it may be worth a try if you are still struggling.

Good luck!