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Xilinx SDK Handling multiple UARTS


pdm

Question

I am working with my new ARTY, and am completely new to Vivado. I am attempting to add multiple 4+ uarts to a project and send them out to external 422 converters. TX and RX on the uart ports will be controlled by my software via TCP packet commands sent from a desktop application. My intent is to start with a networking demo and then add the 4+ uarts to the Vivado design then modify the network demo code. I have built and run both a networking demo, and uart hello world demo. Folks on this form here aided me in getting my tx and rx routed to the header and away from the standard usb uart.

I am sort of lost when it comes to how to proceed with talking to the uarts via the SDK program. I see lots of "hello worlds" for serial stuff, but these circumvent the whole setup process for the code/project. They use a print() that is magically mapped by SDK to the singular uart. Xilinx generates a bunch of libs/code for me, but I am not sure how to go about using the included libraries to talk to the individual. I understand that there is a memory mapping on the AXI bus, but am not sure how to individually address each uart or setup interrupts upon rx.

My Questions:

This seems very complicated knowing little about Xilinx SDK, Is this easier than it seems? Is there a good tutorial on this that I am missing in my internet dredging?

Is starting with a networking demo and adding my uarts and code a good approach, or should I start a project form scratch?

Can someone who has done something similar give me a rough explanation of how to proceed?

 

Thanks in advance,

Paul

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This sounds like a good project for the Arty.  The board should be well up to the task.

That said, yes, it is a complex task.

I know of no one who has accomplished such a task.  However, since very few people feel any need, urge, or inclination to share their projects--this isn't saying much.  The web server tutorial may be the best tutorial/example project out there--even though it doesn't do much with the UARTs you need.

I am personally working on a "starting from scratch" project.  When I say "starting from scratch", that's what I mean: I'm not intending to use any Xilinx IP (although the project currently uses the MIG memory controller).  It doesn't use any Xilinx UART controllers (it uses an open source controller), no MicroBlaze (it uses a ZipCPU), etc.  While I have roughly three UARTs attached to my project (one connected to the PC for controlling the device, one for general UART use, and one connected to a PModGPS), I'm still wrestling with my own version of a DDR3 memory controller and that has kept me from implementing the full network interface.  It's not that the two are dependent on each other, but rather that I have chosen to try to get the memory controller working first.  Sure, I'll get there, but the fact that I'm not there yet might just be a piece of the information you are looking for.

Hope this helps,

Dan

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