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lukap

I2S IP core and AXI DMA

Question

Hello.

I'm doing a sound analyzing project on the Zybo board and I'm having hard time using the AXI DMA for transferring data from the I2S controller to RAM. I'm using the I2S controller from the Digilent's github.

I am trying to do the data transferring "properly" with a DMA and as there are no PL330 examples to be found (at least not bare metal, which is what I'm doing), I'm trying to use the AXI DMA. However I can only get a few samples to the RAM. I don't really know if there's a problem in the I2S controller or in my configuration of the DMA, so I'd first like to know if I understand how the DMA works.

I'm basing my code on the Xilinx' interrupt DMA example, so I think the initializations and similar are done correctly. What I'm unsure of is the following: I start the S2MM (Stream to Memory Mapped - I2S to RAM) transfer with the number of bytes to be transferred and expect the I2S controller to only output data when it has it (similarly as in the Zybo base system example, except that there the fifo status register is checked, but for the streaming interface I expect this to be taken care of in the IP). So if I want to transfer 5 seconds of audio, I start the transfer of

5 s * 48000 samples/s * 2 (channels) * 4 bytes/sample

For now I then wait for the interrupt in which a flag is set, so that I know the transfer has finished. I expect this to last 5 seconds but instead it happens in a couple hundred ms (I don't have an o-scope) and only a few samples arrive.

So is my understanding correct? Has anyone ever tried interfacing the I2S core to an AXI DMA?

Edited by JColvin
edit of original post to match the reply correction from original poster

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Hi @Peter2018,

We do not have a IP core for the Pmod MIC.  We do have VHDL code for the Pmod MIC that I have attached below. You can use the add a module function in i believe Vivado 2016.4 and up to get the vhdl code to work with the axi bus. Here is a project done in Vivado 2017.4 that uses the add a module to a zynq design. Here is a forum thread that describes how one project used the add a module function.

thank you,

Jon

PmodMicRefComp.vhd

PmodMICRefComp.pdf

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Thank you very much.
I did however manage to get the ADI IP I linked to in my previous post working. I had to do some minor changes (removed the drain_process in the streaming tx and enlarged the period_len register). I am intending to post a link to a working project in a few days.
 

Oh, and the number of bytes from the previous post should be (I forgot to consider the bytes per sample - integer):

5 s * 48000 samples/s * 2 (channels) * 4 bytes/sample

Luka

Edited by lukap
edit of the previous post

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Nice that's awesome and I'd love to see your project! One thing I found out that may be helpful is that I found if the DMA max burst size is over 16 bytes, on playback there was a noticeable pop. I think this comes from the Zynq high performance port not being up to the current AXI standard and doesn't support large burst sizes. 

-Sam

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I am doing a pmod MIC project, I am not sure whether the block design and the code are corrected. Could u show me demo with my block design? The pmod AD1 should be the pmod MIC.

Screen Shot 2018-05-09 at 1.15.49 PM.png

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If I just wanna test the pmod MIC in terminal in SDK, what block design will be like and what the c code in SDK? Could you show me the specific demo?   Thx so much!

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Hi @Peter2018,

We did not have time to make an IP core or microblaze demo for the Pmod MIC. All we have for the Pmod MIC is the HDL code. The easiest way to use the Pmod MIC in microblaze/sdk would be using the add a module function.

thank you,

Jon 

 

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Hi @Peter2018,

I would suggest to use the PmodDPG1 IP Core instead of the PmodAD1 IP Core since the PmodDPG1 has the exact pinout on J1 of the PmodMIC(page 2) as well as the same ADC. I believe all you will just need to alter what you do with the data once it has been read in main.

thank you,

Jon

 

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