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SFP over vc709 Board


MOHIT

Question

CONFIGURATION OF  TX AND RX AT THE SAME KIT FOR 32 BIT DATA WITH 8B/10B ENCODING TECHNIQUE ( loop back )

I AM FACING PROB AT THE TIME OF IMPLEMENTATION ,IT IS SHOWING ERROR (PLACE 30-510)

BUT I HAVE USED SAME REFERENCE CLOCK  FOR RX AND TX AS GT-REFERENCE CLOCK DEFINED FOR SAME QUAD(113)

 I AM NOT GETTING HOW TO SOLVE THIS IF ANYONE HAVE EXP PLZ SHARE 

THANKS IN ADVANCE

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I am using virtex 7 vc709 board , in that i want to access the optical fiber i am trying to use si5324 clock as gtrefclock over quad113 that is related to sfp connector 

there are  4 sfp connector at the board ,in that i am using x1y15 as a transmitter and x1y14 as a receiver on the same kit 

so i have generated two core one for tx and one for rx and make one file to intantiate both the core and  one  more file where i am assigning fix 32 bit data for tx and receiving the same data from x1y14 and msb of   that receiving data i am assigning to user leds of board  and remaining at fmc connector but i am getting errror in implementation 

here i am attaching th e error page and my xdc file 

 

and the meaning of this command

set_property LOC GTHE2_CHANNEL_X1Y15 [get_cells gtwizard_tx_support_i/U0/gtwizard_tx_init_i/gtwizard_tx_i/gt0_gtwizard_tx_i/gthe2_i]

 in the place of this keyword  "GTHE2_CHANNEL_X1Y15" i have to define number  or no need to do 

 

 

   Thanks a lot for your response

 

 

 

error.jpg

New Text Document (8).txt

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Hi MOHIT,

Looking at the 30-510 error, I think this post here should help you. Here is link to the user guide for the Virtex 7 vc709 board. We do not have a Virtex 7 vc709 board in house to be able to duplicate your error. We will still do whataver we can to help you but due to not having a Virtex board others in the community might be better able to assist you.

thank you,

Jon  

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On 8/23/2016 at 1:21 AM, jpeyron said:

Mohit,

Please post what version of Vivado/ISE , board i.e. nexys 4 or basys 3 and your project so that we can better assist you. 
Also here is a post that deals with this specific error and some help to fix issue.

thank you,

Jon

Thank you Jon 

but once you can see my xdc file what i am thinking that clock i have assigned correctly but my xdc file is not correct once if you want you can review it please 

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MOHIT

You should try the Xilinx forum to find help on the VC709 as that product.  The digilent guys are very helpful but the Xilinx forum will have a bigger VC709 user community as well as Xilinx staff who know your board.  Also, Xilinx has a tutorials that you can down load for the VC709 that also have example projects with XDC's.

http://www.xilinx.com/products/boards-and-kits/dk-v7-vc709-g.html?resultsTablePreSelect=documenttype:Example

The IBERT tutorial downloads even use Bank113 on the VC709.  You could get the proper XDC from there.  Also note I think you have to jumper SMA jacks J31 and J32 to SMA Jacks J25 and J26 to feed a clock to bank 113 refclk 1.  Or do you have an external clock wired up?

 

Good luck

 

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10 hours ago, FlyingBlindOnARocketCycle said:

MOHIT

You should try the Xilinx forum to find help on the VC709 as that product.  The digilent guys are very helpful but the Xilinx forum will have a bigger VC709 user community as well as Xilinx staff who know your board.  Also, Xilinx has a tutorials that you can down load for the VC709 that also have example projects with XDC's.

http://www.xilinx.com/products/boards-and-kits/dk-v7-vc709-g.html?resultsTablePreSelect=documenttype:Example

The IBERT tutorial downloads even use Bank113 on the VC709.  You could get the proper XDC from there.  Also note I think you have to jumper SMA jacks J31 and J32 to SMA Jacks J25 and J26 to feed a clock to bank 113 refclk 1.  Or do you have an external clock wired up?

 

Good luck

 

thanks alot

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