Hi, The reference manual for the PmodALS states, "The PmodALS requires the frequency of the SCLK to be between 1 MHz and 4 MHz."
However, the TI ADC datasheet doesn't indicate any such restriction. It indicates the recommended SPI SCLK rate is from 25kHz to 20MHz. The PmodALS schematic appears to have direct wiring from the SCLK and SDATA pins to the PMOD connector, as well.
What is the reason the PmodALS reference manual indicates a narrower range, especially a minimum of 1MHz?
(A limited upper limit would be understandable for rise/fall time issues from trace capacitance, etc. Also, since the SAR ADC operates on SCLK, internal leakages could lead to more error at lower rates, but the datasheet doesn't indicate any issue with slower rates in the recommended range.)
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InPhaseDesign
Hi, The reference manual for the PmodALS states, "The PmodALS requires the frequency of the SCLK to be between 1 MHz and 4 MHz."
However, the TI ADC datasheet doesn't indicate any such restriction. It indicates the recommended SPI SCLK rate is from 25kHz to 20MHz. The PmodALS schematic appears to have direct wiring from the SCLK and SDATA pins to the PMOD connector, as well.
What is the reason the PmodALS reference manual indicates a narrower range, especially a minimum of 1MHz?
(A limited upper limit would be understandable for rise/fall time issues from trace capacitance, etc. Also, since the SAR ADC operates on SCLK, internal leakages could lead to more error at lower rates, but the datasheet doesn't indicate any issue with slower rates in the recommended range.)
Thanks, Scott
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