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Nexys4 Ddr Tutorial Question

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Hello,

 

I'm trying to follow the tutorial posted here:

https://reference.digilentinc.com/nexys4-ddr:gsmb

 

I got as far as "Generating Bit File" step. This step fails with the following message in the console:

 

ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 50 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_clock.
ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 50 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: sys_clock.
 
It seems I'm missing some configuration commands which normally go in the *.xdc file, but the tutorial did not specify that an *.xdc file is needed.
 
I'm running Vivado 2014.4 and the board is PB200-292, rev C.
 
Has anybody seen this before?
 
 
 
Edited by Josh
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I ran into this problem.  I ended up simplifying the set_property lines. All the Xilinx xdc files I looked at seemed to do it that way. 

 

From

set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]

 

To

set_property PACKAGE_PIN J15             [get_ports { SW[0] }]

set_property IOSTANDARD LVCMOS33  [get_ports { SW[0] }]

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I managed to finish the tutorial by adding an *.xdc file to the constraints in Vivado. The file contains only this line:

 

set_property -dict { PACKAGE_PIN E3   IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]

 

I'm not sure why the port did not pick up this from the board_part.xml file. The tutorial and/or board definitions should be updated with the correct information.

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Thanks for posting the problem and a fix. I'm really hoping this can be resolved in the tutorial by adding another step that ensures the sys_clock pin is being properly connected from the block diagram to the board_part.xml. I'll keep the XDC fix in mind though as a last resort. 

 

I'll let you know when its fixed.

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