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Arty: Output Frequency

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Greetings!

I recently bought my first Arty (xc7a35ticsg324-1L), and I’m very interested in output signals at high frequencies.

The Arty board includes a single 100 MHz crystal oscillator connected to pin E3. As a first step I want to drive this clock signal to an output pin.

Initially I have tried to use the standard  Pmod connectors to output the clock signal but It doesn´t work because the max supported frequency is 24 Mhz and I get an output waveform very distorted (the frequency is correct but the shape is not square).

Another possibility is to use the high-speed Pmods or the Arduino/chipKIT Shield Connector. I’ve tried but the results were also unsatisfactory, so now I wonder the following question.

What is the highest frequency I can output a clock from Arty board?

Thanks

Fields

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The high speed PMODs can go very fast, but you have to work the way high speed signals work, taking great care.

That may mean differential signalling, correct termination and careful PCB layout. 

I have been able to get 500Mb/s to work, but that also included a good bit of luck.

With single ended signalling you will have very poor results.

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Xilinx recommends using the ODDR primitive, should you wish to output a clock.  As a result, the code you should try will look something like:

ODDR sck(.Q(o_pin), .C(clk), .CE(1'b1), .D1(1'b1), .D2(1'b0), .R(1'b0), .S(1'b0));

If you wish to output a differential clock, you can dump the o_pin output into an OBUFDS to create o_pin_n and o_pin_p outputs which would then go to your differential clock.

The above example comes with a caveat, however: I'm pulling that example from code of my own that doesn't work (yet).  ;)  Your mileage might vary.

Dan

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Thanks, very helpful!

The project is going well, but it doesn´t work yet.

Xilinx recommends clock forwarding to output a clock from FPGA. This means using an ODDR exactly as your recommendation.  I did it for a single-ended clock (10 Mhz) and it works. This is great news but unfortunately differential clocks are very different for me.

Firstly I have used the ODDR and the OBUFDS to convert the single-ended clock to differential. In the Arty Master XDC the differential Pmod JB and JC have LVCMOS33 as IOStandard which can only support single-ended. This is perhaps a little contradictory.

I also have tried to use the LVDS standard, but the LVDS I/O standard is not supported by Arty. I have been thinking about it and this makes me wonder a new question.

What I/O standard I should use to output a differential clock from Arty board?

Best regards

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@Fields,

Hmm ... Good question.  Have you looked through the 7-series Select-IO Resources User Guide?  I just worked my way through the I/O resources guide, and I couldn't find anything that sould support differential I/O at 3.3V.  You might wish to check for yourself, I am by no means authoritative.

You might also wish to create two ODDR's and two OBUF's.  It's a kludge, and it might not work, but ... then again, it might.

Let me know how well it works,

Dan

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