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dnappier

Simple HDMI pass through with NexysVideo

Question

I'm trying to get started with a simple project on the NexysVideo where I simply pass the HDMI signal through. I created the following Block Design:

Capture.PNG

 

The clocking wizard is supposed to be using the 100 external clock on the board.

I am getting the following errors during implementation:

[BD 41-1273] Error running apply_rule TCL procedure: can't read "board_if": no such variable
    ::xilinx.com_bd_rule_mig_7series::apply_rule Line 48

and

[Place 30-149] Unroutable Placement! A MMCM / (BUFIO/BUFR) component pair is not placed in a routable site pair. The MMCM component can use the dedicated path between the MMCM and the (BUFIO/BUFR) if both are placed in the same clock region or if they are placed in horizontally adjacent clock regions. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/I] >

    hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X0Y3
     hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer (BUFR.I) is provisionally placed by clockplacer on BUFR_X0Y17
     hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/SerialClkBuffer (BUFIO.I) is provisionally placed by clockplacer on BUFIO_X0Y16

    The above error could possibly be related to other connected instances. Following is a list of 
    all the related clock rules and their respective instances.

Does anyone have any ideas on how to fix this? It has been a long time since I have done FPGA design and I am very new to this block design methodology from Xilinx. Any help is appreciated.

  

Capture.PNG

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Hi Dnappier, 

The clk wizard and the DVI2rgb both use a mmcm but they are on the same bank (bank 34). So to fix this issue you will need to open the clk_wiz_0 and select clocking options and select pll instead of mmcm. I have attached a fixed project of your design.  

thank you, 

Jon

simple_project_esc.zip

Edited by jpeyron

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Hi @jpeyron,

I tried to use your fixed example in Vivado 2017.4 but I am getting the following error:

 [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

 

Could you please help?

Thank you

Edited by neocsc

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Hi @neocsc,

Please attach a screen shot of the error.  Not all timing errors will break a project. 

1) Are you still able to generate a bitstream or does the timing error force the bitstream generation to stop?

2) If you are able to generate a bitstream please export the hardware(include bitstream), launch sdk and import application. Then program the fpga and run as ->launch on hardware(system debugger). 

3) If so does the project make a serial terminal menu?

$) If so does the project generate a HDMI pass through along with a pre-generated image?

thank you,

Jon

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Hi @jpeyron,

Here is the screenshot of my design. I am also attaching the properties of clock wizard, dvi2rgb and rgb2div.

Bellow is the xdc constraints:

## Clock Signal
set_property -dict { PACKAGE_PIN R4    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_34 Sch=sysclk
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

## HDMI in

#set_property -dict { PACKAGE_PIN AA5   IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L10P_T1_34 Sch=hdmi_rx_cec
set_property -dict { PACKAGE_PIN W4    IOSTANDARD TMDS_33    } [get_ports { TMDS_IN_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
set_property -dict { PACKAGE_PIN V4    IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
create_clock -period 6.734 -waveform {0 3.367} [get_ports { TMDS_IN_clk_p }];
#set_property -dict { PACKAGE_PIN AB12  IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa
set_property -dict { PACKAGE_PIN Y4    IOSTANDARD LVCMOS33 } [get_ports { DDC_scl_io }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
set_property -dict { PACKAGE_PIN AB5   IOSTANDARD LVCMOS33 } [get_ports { DDC_sda_io }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda
#set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_txen }]; #IO_L3P_T0_DQS_34 Sch=hdmi_rx_txen
set_property -dict { PACKAGE_PIN AA3   IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_data_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0]
set_property -dict { PACKAGE_PIN Y3    IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_data_p[0]  }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0]
set_property -dict { PACKAGE_PIN Y2    IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_data_n[1]  }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1]
set_property -dict { PACKAGE_PIN W2    IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_data_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1]
set_property -dict { PACKAGE_PIN V2    IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_data_n[2]  }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2]
set_property -dict { PACKAGE_PIN U2    IOSTANDARD TMDS_33     } [get_ports { TMDS_IN_data_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2]


## HDMI out
#set_property -dict { PACKAGE_PIN AA4   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec
set_property -dict { PACKAGE_PIN U1    IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n
set_property -dict { PACKAGE_PIN T1    IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_clk_p  }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p
set_property -dict { PACKAGE_PIN AB13  IOSTANDARD LVCMOS25 } [get_ports { hdmi_tx_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd
set_property -dict { PACKAGE_PIN U3    IOSTANDARD LVCMOS33 } [get_ports { DDC_scl_io }]; #IO_L6P_T0_34 Sch=hdmi_tx_rscl
set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports { DDC_sda_io }]; #IO_L6N_T0_VREF_34 Sch=hdmi_tx_rsda
set_property -dict { PACKAGE_PIN Y1    IOSTANDARD TMDS_33     } [get_ports {TMDS_OUT_data_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0]
set_property -dict { PACKAGE_PIN W1    IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_data_p[0]  }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0]
set_property -dict { PACKAGE_PIN AB1   IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_data_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1]
set_property -dict { PACKAGE_PIN AA1   IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_data_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1]
set_property -dict { PACKAGE_PIN AB2   IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_data_n[2]  }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2]
set_property -dict { PACKAGE_PIN AB3   IOSTANDARD TMDS_33     } [get_ports { TMDS_OUT_data_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2]


## Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

#---------------------------------------------------------------------------------

 

I am able to generate the bitstream but no signal is detected by the HDMI display. I got stuck in this project. I have seen some threads where they say that one hot plug should be added (I added on at hdmi_tx_hpd) but it did not work.

 

Could you please help me?

Thank you

diagram.png

clk_in.png

clk_out.png

dvi.png

rgb.png

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Hi @neocsc,

I believe you should be using the hdmi_rx_hpa from the master xdc for the Nexys Video here.

#set_property -dict { PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa

thank you,

Jon

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Hi @jpeyron and @kwilber,

still did not work. Could you please provide one working project  for me to test? It is over one week and I am still unable to generate one simple pass-through buffer.

Thank you

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Unfortunately, I do not have a NexysVideo board available. I have run the simple hdmi pass thru on both zybo and arty boards.

Have you tried using a resolution of 720p yet? I find it useful to start with the lower frequencies first. Most sources and monitors have no trouble working with that.

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Here is an archive for the zybo z7 version of a 720p hdmi pass thru I did for someone a few days ago. You should be able to unzip it, open it in vivado and examine it.

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Hi @kwilber,

I was able to compile with no errors or critical warnings the project but it just display no signal detected on the monitor. I also tried 720p and it has the same behavior of 1080p (no signal, just a black screen).

I will further analyze your project.

Thank you.

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Hi @neocsc,

Here is a verified Nexys Video HDMI project updated from Vivado 2016.4 to Vivado 2017.4. You should be able to find the updated project in the proj folder .  Here is a GitHub project done in HDL using the clocking wizard, DVI2RGB and RGB2DVI IP Cores for another FPGA.  Here is a unverified Nexys Video Vivado 2017.4 HDMI pass through project made from the linked Github project. In the next few days I should have the bandwidth to verify this project.

thank you,

Jon

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Hi @jpeyron,

thank you very much for this. I was able to run the HDMI video but when I try to get the pass-through mode there is only a black screen. I was also able to do a simple pass-through video with no critical warnings or errors but still no signal is detected. 

My configuration is as follows: ASUS laptop is sourcing the HDMI in to the FPGA and one iiyama monitor is being used to display. I did test with different resolutions several projects but only the default bitstream from the FPGA is working properly.

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Posted (edited)

Hi everyone,

thank you for the explanations and details already here. I have a Nexys Video that I received today and I have the following diagram for the passthrough buffer. My clock wizard is setup to 125Mhz. DVI2RGB is for 1080p clk >= 125MHz. Same for RGB2DVI.

 

My problem is: If I set RGB2DVI as PLL I got the following error:

[Labtools 27-3428] Ila core [hw_ila_1] clock has stopped. Unable to arm ILA core.

Otherwise, if MCMM is setted, than I get this error:

[Place 30-149] Unroutable Placement! A MMCM / (BUFIO/BUFR) component pair is not placed in a routable site pair. The MMCM component can use the dedicated path between the MMCM and the (BUFIO/BUFR) if both are placed in the same clock region or if they are placed in horizontally adjacent clock regions. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/I] >

 

Could anyone, please help me?

Best regards,
Carlos

I have the following xdc constraints:

[Labtools 27-3428] Ila core [hw_ila_1] clock has stopped. Unable to arm ILA core.

### This file is a general .xdc for the Nexys Video Rev. A
### To use it in a project:
### - uncomment the lines corresponding to used pins
### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project


## Clock Signal
set_property -dict { PACKAGE_PIN R4    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_34 Sch=sysclk
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

## System Reset
set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS12 } [get_ports { rst }]; #IO_L20N_T3_16 Sch=btnc

## HDMI in
set_property -dict { PACKAGE_PIN W4    IOSTANDARD TMDS_33  } [get_ports { hdmi_in_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
set_property -dict { PACKAGE_PIN V4    IOSTANDARD TMDS_33  } [get_ports { hdmi_in_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
create_clock -period 6.734 -waveform {0 3.367} [get_ports { hdmi_in_clk_p }];

set_property -dict { PACKAGE_PIN AB12  IOSTANDARD LVCMOS25 } [get_ports { hdmi_in_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa

set_property -dict { PACKAGE_PIN Y4    IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_scl_io }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
set_property -dict { PACKAGE_PIN AB5   IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_sda_io }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda

set_property -dict { PACKAGE_PIN AA3   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0]
set_property -dict { PACKAGE_PIN Y3    IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_p[0] }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0]
set_property -dict { PACKAGE_PIN Y2    IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_n[1] }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1]
set_property -dict { PACKAGE_PIN W2    IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1]
set_property -dict { PACKAGE_PIN V2    IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_n[2] }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2]
set_property -dict { PACKAGE_PIN U2    IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2]


## HDMI out
#set_property -dict { PACKAGE_PIN AA4   IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec
set_property -dict { PACKAGE_PIN U1    IOSTANDARD TMDS_33  } [get_ports { hdmi_out_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n
set_property -dict { PACKAGE_PIN T1    IOSTANDARD TMDS_33  } [get_ports { hdmi_out_clk_p }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p
set_property -dict { PACKAGE_PIN AB13  IOSTANDARD LVCMOS25 } [get_ports { hdmi_out_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd

set_property -dict { PACKAGE_PIN Y1    IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0]
set_property -dict { PACKAGE_PIN W1    IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[0] }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0]
set_property -dict { PACKAGE_PIN AB1   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1]
set_property -dict { PACKAGE_PIN AA1   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1]
set_property -dict { PACKAGE_PIN AB2   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[2] }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2]
set_property -dict { PACKAGE_PIN AB3   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2]


## Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

image.thumb.png.194663813bbfdf7c9550bb490612530f.png

 

image.png

Edited by john_joe

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Posted (edited)

Interesting that I re-targeted the project to a Zybo Z7-20 and the project runs without problem when RGB2DVI is marked as PLL and I can reproduce the screen of my laptop on the monitor at 1080p.

Edited by john_joe

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Posted (edited)

Dear @jpeyron,

thank you!

 

The Nexys Video HDMI project works as well as the default demo from the board.

Regarding to the simple pass through buffer,

when the clocking wizard and RGB2DVI is both configured as PLL the bit-stream is successfully generated.  I am even able to see the ILA core with a message "no content". However, when I press play the "ILA clock stopped" message is shown and no signal detected is displayed on the screen. Otherwise, if the MMCM is setted instead in the DVI2RGB, the bad routing message is displayed and I am not able to generate the bit-stream.

 

I really need this simple project working instead a larger one such as the demo that comes available from the link you posted. I am curious why this project, properly re-targeted to a Zybo Z7-20, runs without any problem.

One more time, I do appreciate your support. 

Edited by john_joe
adding more details

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Hi @john_joe,

Typically having both the RGB2DVI and the Clocking wizard set to PLL causes a  Unroutable Placement error in vivado. If vivado allows you to have both the clocking wizard and the RGB2DVI set to PLL then your project should be fine. 

Does the pass though work with this project?

best regards,

Jon

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Posted (edited)

Dear @jpeyron,

To summarize my problem:

On nexys video: Clocking Wizard: PLL and RGB2DVI:PLL ==> bitstream is generated but no signal detected on screen and ILA core clock stopped

                             Clocking Wizard:MMCM or RGB2DVI:MMCM ==> unroutable placement error message

 

On zybo z7-20 : Clocking Wizard: PLL and RGB2DVI:MMCM ==> bitstream is generated and project works perfectly. Video is streamed on the screen.

 

I am without understanding why the Nexys Video does not work.

 

PS: I am not sure if it is relevant but I am using Vivado 2018.3  on a Windows 10 machine. The RGB2DVI version is 1.4 and DVI2RGB version is 1.9

 

Thank you. 

Edited by john_joe

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Hi @jpeyron,,

many thanks for the support. Unfortunately your bitstream file does not work on my board. I also generated the bitstream from your project. No signal is detected on my screen. I am frustrated because I can't understand why.

However, I was able to get the board working with this project that I found on Github: https://github.com/hamsternz/Artix-7-HDMI-processing

Best regards.

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