In Vivado versions 2015.X-2016.2 there is a bug in the AXI_GPIO Core when adding a board part to the GPIO2 interface on the AXI_GPIO IP block in Vivado IPI (block design). You may get the following error:
[IP_Flow 19-3452] Invalid long/float value '16]' specified for parameter 'GPIO Width(C_GPIO2_WIDTH)' for BD Cell 'axi_gpio_0'.
To fix this go into Vivado/2016.2/data/ip/xilinx/axi_gpio_v2_0/xgui/axigpio_v2_0.tcl and remove the extra ']' at the end of line 246.
Hopefully Xilinx will fix this small typo in the 2016.3 release.
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TommyK
In Vivado versions 2015.X-2016.2 there is a bug in the AXI_GPIO Core when adding a board part to the GPIO2 interface on the AXI_GPIO IP block in Vivado IPI (block design). You may get the following error:
[IP_Flow 19-3452] Invalid long/float value '16]' specified for parameter 'GPIO Width(C_GPIO2_WIDTH)' for BD Cell 'axi_gpio_0'.
To fix this go into Vivado/2016.2/data/ip/xilinx/axi_gpio_v2_0/xgui/axigpio_v2_0.tcl and remove the extra ']' at the end of line 246.
Hopefully Xilinx will fix this small typo in the 2016.3 release.
Hope this helps!
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