Gigabit Ethernet

[agdiaz1]

Hello, I am a student of electrical engineering, and I am using a Genesys board with a Virtex-5 to try to send information and Gigabit Ethernet speed. Previously I was working with the Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper Core at MII speed and managed to learn from the example design provided (the address swap module). However, the example design that comes with the Core at GMII speed comes with more clock requirements that are difficult to implement. How can manage the constraints for all the clocks that are needed to make this example to work? 

 

 

Can somebody help me with making the example design work?.  

[elodg]

Did you look in the Ethernet demo project for the Genesys to see how the clocks are connected and constrained there?

http://digilentinc.com/Data/Products/GENESYS/Genesys_Lwipdemo.zip

 

The TEMAC Wrapper Getting Started Guide too might be useful: http://www.xilinx.com/support/documentation/ip_documentation/v5_emac/v1_8/v5_emac_gsg340.pdf

Appendices B and C talk about the different clocking configurations for certain interface/speed combinations and how to constrain them. Are you trying to achieve 1000Mbps speeds over the GMII interface?

[elodg]

Could you point me to the exact example you are talking about? Also, posting specific questions rather than "manage the constraints" will increase your chances that someone will pick up your question. Is there an error you are getting, or perhaps a step you are stuck at?

[agdiaz1]

Well, when I make a new IPCore, select the Communication & Networking/Ethernet/Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper, and select the GMII Phy interface I get a bunch of modules that are the example design. The top module makes an instantiation of the module address_swap_module_8 along with many others, but the idea of this specific one is that it interchanges the MAC addresses of a packet that goes into the FPGA through the Gigabit Ethernet. So a successful test would be see a ARP packet that comes from a computer returned to it with the MAC addresses swapped (seeing the packets in Wireshark). However, in order to make this work I need to be able give this example design the correct clocks and that is where I am stuck, because I have tried many ways I can think of but I can't manage to get it to work. 

[Ragavesh]

Hi,

I am trying to activate Ethernet and develop simple test application with XPS(14.5) and EDK(14.5). I have tried to use follow the tutorial provided with IP core for GENESYS board. The synthesis getting over, however when peripheral test app is not working in EDK.

After referring few site, i have tried own project using BSP. I have chosen the following configuration

1. Microblaze with i and d cache - DDR2

2. DDR2 - 2GB - Tested separately - it is working

3. GPIO such as (LCD, LED, Push button, Switches) - All are tested with memory and separately - it is working

4. SYSMON - ADC - tested only to check core temperature - working with Sl 1 to 4.

5. Ethernet - After adding this IP, the synthesis ran for more than 3hrs! and ended up with device is full!!

Note, I have modified the design with interrupt, DMA. 

My Question is: Any specific project in-line to these peripheral? or any EDK examples for 14.5? The reference design provided including lwipdemo is not working with 14.5.

 

[sbobrowicz]

Hi Ragavesh,

I think you need to be using the ethernet core that is specifically designed for the Virtex 5 (see the above posts). The Virtex5 actually has a "hard" TEMAC that the core needs to instantiate. Using the ethernet core designed for other devices (like newer 7 series devices that work in 14.5) would cause the TEMAC to be implemented in fabric and increase the resource utilization as you have seen.

The Genesys is being phased out for the Genesys2, and will be discontinued in the not too distant future. For this reason, it is not likely that Digilent will be designing new applications/demos for it that target the newer tools. Sorry for the inconvenience.