The code below is from the textbook "Digital Design Using Digilent FPGA Boards Active -HDL Edition by Haskell & Hanna" on page 151. The input variable "x" is multiplied by decimal value "100" (7-bit). The results will be assigned to output variable "p".
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity mult100 is
Port ( x : in STD_LOGIC_VECTOR(8 downto 0); --9 bit
p : out STD_LOGIC_VECTOR(15 downto 0)); --16 bit
end mult100;
architecture Behavioral of mult100 is
begin
p <= '0' & x & "000000" --shift 6 bit left, line 48
+ "00" & x & "00000" --shift 5 bit left
+ "00000" & x & "00";--shift 2 bit left
end Behavioral;
The error shown in ISE 13.2 is "Line 48: Expression has 41 elements ; expected 16
Netlist mult100(Behavioral) remains a blackbox, due to errors in its contents"
I found this issue can be solved by declaring three signals, "a", "b", and "c" and implemening the multiplier as follow. But I don't know why the original code doesn't work. Thank you.
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eflyzhao
The code below is from the textbook "Digital Design Using Digilent FPGA Boards Active -HDL Edition by Haskell & Hanna" on page 151. The input variable "x" is multiplied by decimal value "100" (7-bit). The results will be assigned to output variable "p".
The error shown in ISE 13.2 is "Line 48: Expression has 41 elements ; expected 16
Netlist mult100(Behavioral) remains a blackbox, due to errors in its contents"
I found this issue can be solved by declaring three signals, "a", "b", and "c" and implemening the multiplier as follow. But I don't know why the original code doesn't work. Thank you.
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