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Wolf0

Possibly faulty Nexys Video

Question

I have had a Nexys Video for quite a while. I first thought this was normal behavior for the XC7A200T, but once I got an XC7K325T - and it does not demonstrate this - I started to think otherwise.

 

The behavior leading me to think it's faulty is this: I am hashing Blake-256 on it. When I use 4 cores of my design (as I use with my XC7A100T on my Nexys 4 DDR) it works fine. Now, this packs the XC7A100T mostly full, but the 200T still has room. So, I've tried packing 7 on it, as well as 8. While the bitstream is made fine, it fails upon flashing. It won't take more than six. I tried raising the clock just a bit - same issue. It's almost as if parts of the FPGA just don't want to be flashed or work. The XC7K325T, by the way, takes 12 cores so far at 150Mhz.

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I have had the same behaviour on a very full design. I put it down to drawing too much power from the power supplies causing the FPGA to reset.

Not sure if this is 100% what is going on, but a smaller design worked fine.

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33 minutes ago, hamster said:

I have had the same behaviour on a very full design. I put it down to drawing too much power from the power supplies causing the FPGA to reset.

Not sure if this is 100% what is going on, but a smaller design worked fine.

If this is a bug, I'd like a fixed Nexys Video. I wanted to use it for seeing what an XC7A200T could do, in preparation for custom PCB stuff, but as it stands, it looks like it's a pretty minimal upgrade from an XC7A100T if the latter can be packed with a full design and the former cannot.

EDIT: Even packed 14 cores to the XC7K325T.

Edited by Wolf0
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Hi Wolf0,

The thing you are encountering is not a bug, but the limitation of the design. When you have a very large project that would take a large part of the FPGA capability and at a high frequency the FPGA starts consuming power. If it goes above the maximum current the source provides, the board resets. In the board reference manual you can find a table of what the power sources care capable to supply. Vivado can estimate the power consumption of your design. You can check that and compare it with the values provided in the table of the power sources. If the value provided in Vivado is higher than the value in the table, there's the problem. 

Best regards,

Bianca

 

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On 07/18/2016 at 7:02 AM, Bianca said:

Hi Wolf0,

The thing you are encountering is not a bug, but the limitation of the design. When you have a very large project that would take a large part of the FPGA capability and at a high frequency the FPGA starts consuming power. If it goes above the maximum current the source provides, the board resets. In the board reference manual you can find a table of what the power sources care capable to supply. Vivado can estimate the power consumption of your design. You can check that and compare it with the values provided in the table of the power sources. If the value provided in Vivado is higher than the value in the table, there's the problem. 

Best regards,

Bianca

 

Thank you! This is helpful - is there any way to raise the power available? Probably by bumping the voltage just a bit?

Edited by Wolf0

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Unfortunately most of the regulators are fixed and the programmable one already works at full capacity (4A). Just by increasing the voltage, won't help you. The current is already maximum.

Regards,

Bianca

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Hi,

I had the same problem, with a high-frequency design that uses most of the A200T : Maximum power consumption on the Nexys Video. The 1.0V rail on the Nexys Video is limited to 4A (one output of an ADP5052). On the Genesys 2, the voltage regulator is much beefier and can provide up to 14A on the 1.0V rail.

The only solution I see is lowering the frequency (works surprisingly well as most of the power consumption comes from dynamic power). Even though this prevents you from using the full power of the FPGA, you can at least check that your large design behaves as expected (and do performance assessment on another board).

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