I am currently using CMOD S6 to generate 12 bit data logic and clock for a DAC. The clock frequency is at 50 MHz which was created using DCM ip core in ISE. I then output the clock from pin 48. However I am having a bit of ground noise issue. The clock signal seem to be coupling onto the as the noise I observe on the oscilloscope is at around 50MHz with 500mVp-p on digital ground. In order to reduce this noise I have tried lower frequency at 10MHz (but for my application I really need it at 50MHz) and also used coaxial cable to connect the FPGA output and DAC. I am testing these on a prototype board so there will of course be additional noises but I get the feeling that CMOD S6 may not be able to support such frequency output. For instance when I tried to test just the CMODS6 on bread board the clock signal coupled onto ground as well.
PCB implementation may eliminate this issue but I just want to hear from the Digilent if the CMODS6 can support 50MHz signal output.
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deltadia
Hi,
I am currently using CMOD S6 to generate 12 bit data logic and clock for a DAC. The clock frequency is at 50 MHz which was created using DCM ip core in ISE. I then output the clock from pin 48. However I am having a bit of ground noise issue. The clock signal seem to be coupling onto the as the noise I observe on the oscilloscope is at around 50MHz with 500mVp-p on digital ground. In order to reduce this noise I have tried lower frequency at 10MHz (but for my application I really need it at 50MHz) and also used coaxial cable to connect the FPGA output and DAC. I am testing these on a prototype board so there will of course be additional noises but I get the feeling that CMOD S6 may not be able to support such frequency output. For instance when I tried to test just the CMODS6 on bread board the clock signal coupled onto ground as well.
PCB implementation may eliminate this issue but I just want to hear from the Digilent if the CMODS6 can support 50MHz signal output.
Many thanks
Jay
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