JerryG Posted July 15, 2016 Share Posted July 15, 2016 Anyone have or know of an example of how to configure a clock using a PLL on the Arty? I'd prefer a small, simple, example rather than some huge project involving MicroBlaze, etc. Link to comment Share on other sites More sharing options...
BKallaher Posted July 15, 2016 Share Posted July 15, 2016 I would recommend using the Clocking Wizard. This tool does not need to be used in a block design. Here is a PDF on the wizard: http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf BKallaher Link to comment Share on other sites More sharing options...
D@n Posted July 15, 2016 Share Posted July 15, 2016 Here's some code from one of my projects. It configures two clocks--a main clock to drive the board at 200MHz, and a secondary clock to drive the RAM that is offset in phase by 90 degrees. The other clocks are unnused. PLLE2_BASE #( .BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW .CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64) .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360) .CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128) .CLKOUT0_DIVIDE(4), // 200 MHz .CLKOUT1_DIVIDE(4), // 200 MHz .CLKOUT2_DIVIDE(8), // 100 MHz .CLKOUT3_DIVIDE(16), // 50 MHz .CLKOUT4_DIVIDE(32), // 25 MHz .CLKOUT5_DIVIDE(16), // CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT .CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT3_DUTY_CYCLE(0.5), .CLKOUT4_DUTY_CYCLE(0.5), .CLKOUT5_DUTY_CYCLE(0.5), // CLKOUT0_PHASE -- phase offset for each CLKOUT .CLKOUT0_PHASE(0.0), .CLKOUT1_PHASE(90.0), .CLKOUT2_PHASE(0.0), .CLKOUT3_PHASE(0.0), .CLKOUT4_PHASE(0.0), .CLKOUT5_PHASE(0.0), .DIVCLK_DIVIDE(1), // Master division value , (1-56) .REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999) .STARTUP_WAIT("FALSE") // Delayu DONE until PLL Locks, ("TRUE"/"FALSE") ) genclock( // Clock outputs: 1-bit (each) output .CLKOUT0(i_clk), .CLKOUT1(clk_for_ddr), .CLKOUT2(clk2_unused), .CLKOUT3(clk3_unused), .CLKOUT4(clk4_unused), .CLKOUT5(clk5_unused), .CLKFBOUT(clk_feedback), // 1-bit output, feedback clock .LOCKED(clk_locked), .CLKIN1(i_clk_100mhz), .PWRDWN(1'b0), .RST(1'b0), .CLKFBIN(clk_feedback) // 1-bit input, feedback clock ); (I'm not one for using the Xilinx wizards ...) Dan Link to comment Share on other sites More sharing options...
hamster Posted July 15, 2016 Share Posted July 15, 2016 Oh, and to go along with Dan's answer... The more recent versions of Vivado seem to have become much more picky about the use of clock buffers, throwing errors if you don't include them. Here's one example of using global clock buffers: library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; entity clocking is Port ( clk100MHz : in STD_LOGIC; clk125MHz : out STD_LOGIC; clk125MHz90 : out STD_LOGIC); end clocking; architecture Behavioral of clocking is signal clk100MHz_buffered : std_logic := '0'; signal clkfb : std_logic := '0'; signal clk125MHz_unbuffered : STD_LOGIC; signal clk125MHz90_unbuffered : STD_LOGIC; begin bufg_100: BUFG port map ( i => clk100MHz, o => clk100MHz_buffered ); ------------------------------------------------------- -- Generate a 125MHz clock from the 100MHz -- system clock ------------------------------------------------------- pll_clocking : PLLE2_BASE generic map ( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT => 10, CLKFBOUT_PHASE => 0.0, CLKIN1_PERIOD => 10.0, -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128) CLKOUT0_DIVIDE => 8, CLKOUT1_DIVIDE => 20, CLKOUT2_DIVIDE => 40, CLKOUT3_DIVIDE => 8, CLKOUT4_DIVIDE => 16, CLKOUT5_DIVIDE => 16, -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999). CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT2_DUTY_CYCLE => 0.5, CLKOUT3_DUTY_CYCLE => 0.5, CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5, -- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000). CLKOUT0_PHASE => 0.0, CLKOUT1_PHASE => 0.0, CLKOUT2_PHASE => 0.0, CLKOUT3_PHASE => -270.0, CLKOUT4_PHASE => 0.0, CLKOUT5_PHASE => 0.0, DIVCLK_DIVIDE => 1, REF_JITTER1 => 0.0, STARTUP_WAIT => "FALSE" ) port map ( CLKIN1 => CLK100MHz_buffered, CLKOUT0 => CLK125MHz_unbuffered, CLKOUT1 => open, CLKOUT2 => open, CLKOUT3 => CLK125MHz90_unbuffered, CLKOUT4 => open, CLKOUT5 => open, LOCKED => open, PWRDWN => '0', RST => '0', CLKFBOUT => clkfb, CLKFBIN => clkfb ); bufg_125Mhz: BUFG port map ( i => clk125MHz_unbuffered, o => clk125MHz ); bufg_125Mhz90: BUFG port map ( i => clk125MHz90_unbuffered, o => clk125MHz90 ); end Behavioral; Link to comment Share on other sites More sharing options...
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JerryG
Anyone have or know of an example of how to configure a clock using a PLL on the Arty?
I'd prefer a small, simple, example rather than some huge project involving MicroBlaze, etc.
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