BASYS3 with Microblaze in Vivado 16.x

[abcdef]

I have been trying to implement a simple Hello World program using a Microblaze IP on a BASYS3 board using Vivado 16.1 and 16.2.  I have had success using the Microblaze MCS design shown in figure mb1.pgn below, which shows that the board and interface works.  However, after many attempts I have never been able to get the design working using a Microblaze, as shown in image mb2. png below.

My simple question is, has anyone gotten the Microblaze to work on a BASYS3 using the free Web version of Vivado 16.1 or 16.2?

Here is some additional information, for anyone interested:

To get the Microblaze MCS design to work, it’s important that "reset" is set to Active High.  Also, when creating the ELF file I use the following approach which seems to work fine in Vivado 16.x:

  Create the complete block design and the design wrapper; run synthesis and then File / Export the Hardware (without including the bitstream;)    then File / Launch SDK.  In SDK, use File / New Application Project and select the Hello World application.  After SDK creates (automatically) the ELF file, associate it in Vivado with the design under Tools \ Associate ELF file; finally, in Vivado generate the bitstream and then in the Hardware Manager program the BASYS3 board and observe the UART output with a terminal program.

As I said, this seems to work without any problems with the Microblaze MCS but not the Microblaze.  Strangely, the Microblaze design does not create any error messages or obvious warnings.  Greatly appreciate any insight. Thanks.

[ewhansen]

On 7/12/2016 at 7:14 PM, jpeyron said:

I was able to get the microblaze "hello world" working for the Basys 3. Microblaze set to 128kb for local memory and no cache config.  I needed to add a new processor system reset and change all of the wires from the rst_clk_wiz_0 100m to it. Make sure to have the reset set to active high in the clock wiz and the ext_reset_in in the processor system reset. Click into the Processor System Reset in the basic section make sure the Ext Reset Logic Level(Auto) is set to 1.  I am also making a Getting started with microblaze tutorial.

 

I have been trying to do the same thing, following the "Basys 3 Getting started in Microblaze" tutorial, https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-getting-started-with-microblaze/start.  I've had a number of problems, having to do with the polarity of the external reset signal:

• When customizing the Processor System Reset block, the polarity of ext_reset_in is grayed out, and defaulted to active-low.  I cannot set it to active-high.  It's as though a generic cannot be overridden.
• The external reset port must be active-high (that's how the button is wired), and consequently wiring the port to the PSR block results in a Validation error (polarity mismatch).
• If the validation error is ignored, the design still synthesizes, etc, without error.  However, when I get to the "Run as" step in SDK, I get an error that the Microblaze is being held in reset (as expected, if the ext_reset_in input is indeed active-low).  
• If I hold the reset button (BTNC) down while trying "Run as", just to see what happens, I get an error that the Microblaze is not being clocked.  Again, this is expected behavior since the Clocking Wizard is now being held in reset.
• The solution would seem to be to put an inverter between the reset port and the PSR block.  This fixes the validation error, but interestingly, after pushing the design through bitstream, etc, the "Run as" still throws a "not clocked" error.

There are a few moving parts here, I realize, and the solution is probably something simple.  I will be grateful to know the answer.

[abcdef]

With JPeyron's advice I was able to get my designs working on the BASYS3. I have very detailed instructions, with a lot's of screenshots on my wiki: https://sites.google.com/a/umn.edu/mxp-fpga/home/vivado-notes/home-vivado-notes-xilinx-vivado-design-suite-16-2-and-embedded-processing-using-microblaze/xilinx-vivado-design-suite-16-2-and-embedded-processing-using-microblaze-with-basys3-simple-hello

Good luck.

[jpeyron]

Hi ewhansen,

Our board files were set up wrong for the reset and were fixed around the time period of the forum question you have posted on. So if you re-install the board files from here your design should work exactly like the tutorial here. Sorry for the inconvience.

cheers,

Jon

[ewhansen]

@jpeyron, I think the board files you pointed me to are the same ones I initially downloaded.  The polarity of the reset port (BTNC) is easily fixed, but the bug in Xilinx' PSR block is nastier.   @abcdef, Thank you for the detailed notes, I was able to get it working.  The key appears to be manually wiring the reset port to the ext_reset_in port of the PSR.  In addition to this fix, your implementation differs at other points from jpeyron's tutorial.  I'd be interested to know if your flow fixes other problems or is just the way you prefer to do things.  Again, many thanks to both of you for creating this basic Microblaze setup on the Basys3.  On to fancier things.

 

[neha]

On 7/13/2016 at 4:44 AM, jpeyron said:

Hi abcdef,

I was able to get the microblaze "hello world" working for the Basys 3. Microblaze set to 128kb for local memory and no cache config.  I needed to add a new processor system reset and change all of the wires from the rst_clk_wiz_0 100m to it. Make sure to have the reset set to active high in the clock wiz and the ext_reset_in in the processor system reset. Click into the Processor System Reset in the basic section make sure the Ext Reset Logic Level(Auto) is set to 1.  I am also making a Getting started with microblaze tutorial.

I am not able change ext reset logic level to 1 in my its 0 and its disable from click. what to do?

[jpeyron]

Hi @neha,

You do not need to do the above process to get the hello world to work. At the time our board files were set up wrong for the reset and were fixed around the time period of the forum question you have posted on. If you recently installed the board files from here your design should work exactly like the tutorial here. Sorry for the inconvenience.

cheers,

Jon

[jpeyron]

Hi @neha,

Do you have a current installation of the board files installed in vivado 2015.2 ? If so when you make your project are you selecting the arty board?  I have taken a screen shot of where I have the files installed and of the available boards you can select from in vivado when making a new project. Can you please attach a screen shot of your board files folder? If you have the board files installed correctly the only thing in the xdc should be :

  set_property -dict { PACKAGE_PIN G18    IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #         Sch=eth_ref_clk 

If you are following our tutorial you will not need to constrain the Ethernetlite pins. The board files do that for you.

cheers,

Jon

[jpeyron]

Hi @neha,

So I had to delete the processor system reset_0 and  add a new processor system reset and change all of the wires from the rst_clk_wiz_0 100m to it. Make sure to have the reset set to active high in the clock wiz and the ext_reset_in in the processor system reset. Click into the Processor System Reset in the basic section make sure the Ext Reset Logic Level(Auto) is set to 1. What board are you using? If you are using the Basys 3 are you also using the PmodNIC100 here? Also if you are using the board files for the basys 3 when you add and configure the Microblaze processor should automatically sets the reset to high.

cheers,

Jon

[neha]

@JPeyron   tnx for reply

I am using arty board.

Thing is that Ext reset Logic  is by default in active low and i am unable to change it, and this is my issue how to make Ext Reset logic active high

[jpeyron]

Hi @neha,

The Ext reset Logic for the Arty should be active low. The red reset button on the Arty when pressed goes low. I have attached a screen shot of this circuit from the schematic here. We have a tutorial that walks users through setting up an echo server using the AXI EthernetLite block on the Arty Artix-7 board here. The Arty resource page is here which has the reference manual, schematic, tutorials, community projects, links to the board files, xdc file and the 3D CAD model and Here is a link to our Github.

[neha]

 @jpeyron Thank you for reply ... 

[neha]

 @jpeyron Thank you for reply ... 

i did with  active low with same process as u mentioned but bitstream error  is coming... I am attaching screen shot

[jpeyron]

Hi @neha,

What version of Vivado are you using? Could you also include a screen shot of your block design. I went through the getting started with Microblaze servers tutorial here in Vivado 2016.4 with no issue. I attached the project below. Vivado will connect your system reset to sys_rst on the MIG.  If you are using Vivado 2015 or below you need to make sure that you Connect this new reset port to the resetn input on the Clock Wizard block as described in the tutorial.

cheers,

Jon

Arty_echo.zip

[neha]

Hi @ jpeyron

 I am using vivado 2015.2.

thank you for making arty tutorial. I follow your tutorial  thoroughly, Implementation have lots error . The line You mention for .xdc file generating  a file of mig_7 series file. In order to remove error I made some changes.

1 I replaced all SPLIT with LVCMOS33

2. As per sch. I tried to change some pin

and in my version vivado in mig7 series to port of clk is coming 1 for 1 for n. ref and sys clk  npin i assigned with  external port.

 

arty_sch.pdf

[jpeyron]

Hi @neha,

In your xdc file I did not see this line:  set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; # Sch=eth_ref_clk   in section 8.4 in the tutorial here has you make the xdc file eth_ref_clk and add that line to it. Have you installed the board files? The board files should constrain everything that you are constraining in the xdc file you took a screen shot of. In older versions of Vivado it looks like when you drag the Ethernet MII it does not create and axi ethernetlite IP block.I attached the IP block that it does create below. Make sure that you are using the axi ethernetlite IP. I have attached a screen shot of my block design as well. Looking at your block design I did not see that the axi ethernetlite was an issue.  I downloaded Vivado 2015.2 and went through the tutorial.I have added my project below. Try running my project and see if you are able to get it running.  

cheers,

Jon

Arty_echo_ethernetlite.zip

[neha]

@jpeyron thanks going to  my  problem , making arty tutorial, installing 2051.2 vivado.

I am facing  problem in generating bit stream as shown in below attachment .I tried run your given  file but some archive problem is with that file .

after adding all Ethernet pins in xdc file  I am able to generate bitstream, as per your tutorial in step 11 some error is coming to generating bsp file. I try to mapped ethernetlite axi port as shown in msg.png, It already mapped now but its not validating  I tried 2-3 times .

Even port is mapped message box popped with not mapped, some how it not upadating