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BASYS3 with Microblaze in Vivado 16.x

Question

I have been trying to implement a simple Hello World program using a Microblaze IP on a BASYS3 board using Vivado 16.1 and 16.2.  I have had success using the Microblaze MCS design shown in figure mb1.pgn below, which shows that the board and interface works.  However, after many attempts I have never been able to get the design working using a Microblaze, as shown in image mb2. png below.

My simple question is, has anyone gotten the Microblaze to work on a BASYS3 using the free Web version of Vivado 16.1 or 16.2?

Here is some additional information, for anyone interested:

To get the Microblaze MCS design to work, it’s important that "reset" is set to Active High.  Also, when creating the ELF file I use the following approach which seems to work fine in Vivado 16.x:

  Create the complete block design and the design wrapper; run synthesis and then File / Export the Hardware (without including the bitstream;)    then File / Launch SDK.  In SDK, use File / New Application Project and select the Hello World application.  After SDK creates (automatically) the ELF file, associate it in Vivado with the design under Tools \ Associate ELF file; finally, in Vivado generate the bitstream and then in the Hardware Manager program the BASYS3 board and observe the UART output with a terminal program.

As I said, this seems to work without any problems with the Microblaze MCS but not the Microblaze.  Strangely, the Microblaze design does not create any error messages or obvious warnings.  Greatly appreciate any insight. Thanks.

mb1.png

mb2.png

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@jpeyron Hi

I want to change something/adding some string in tcp_recved(highlight in blue) follow "he.png",as per as tcp_recved  function include as header file(header.png) , so If I have to change something/add I have to change in header file but if go in left side of picture in include folder there is a purple folder for echo server.

I can not go through that one to make changes

thanks

header.png

he.png

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Hi @neha,

In the sdk you should not be altering the purple folder but rather the echo.c in the src folder below.Unfortunately, I have not had much time to work on sending data through the Ethernet.  I have attached an altered echo.c that responds to humidity and temperature typed in the serial terminal. 

cheers,

Jon

echo.txt

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@jpeyron Hi  want some help in vivado ,generating board file in vivado via ip (I am trying to   implement fft) how to connect all pin to each other. How we use ip catalog ??

help me

 

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Hi @neha,

I unfortunately have not used Xilinx's fft IP. The Xilinx user guide for the IP is where we usually turn when looking on how to work with a specific IP. Here is the Fast Fourier
Transform v9.0 LogiCORE IP Product Guide. Here is a project that I believe uses the Xilinx fft IP with HDL. This might not be exactly what you are looking for since it is with HDL but it should show you what pins connect to what.

cheers,

Jon

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@jpeyron 

hi

I am implementing Ethernet server via above mention steps, but I am not using ddr3 for memory instead  that i am using flash memory.I am getting failed timing message with implementation complete .clock 1(166.667 mhz) of clocking wizard is connected exi_spi_clk, clock2(200 mhz ) with s_axi_aclk and clock 3(25 mhz )  as mentioned doc.
two processor reset create , 200 mhz processor  exi_reset and mb_debug_sys_reset is connected  with exi_reset and mb_debug_sys_reset of 166_reset processor respectively. aresetn of flash is connected with pheripheral arsetn of 200_processor_reset.

xdc file is shown in pic 1

latter i tried also make 4 port concat and connect  port 2 and port 3 to interrupt of uart and axi_quad_spi . I am able to generate bit stream too now, earlier bitstream was not generating. while launching sdk some  system.mss file is not generating

please guide me

pic1.png

pic2.png

pic3.png

Edited by neha
I tried some other option too

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@jpeyron

Greeting

Ok thank you,

But I  Have some question it is possible in this way or not(i mean using flash memory).

 

, As you seen above  there was timing fail  but implementation complete  is coming, basically  there is negative slack i.e;  set up -4.149 ns,hold 0.49 ns , WNS :-4.149 ns, TNS -2863.596 ns. How to remove negative slack/ timing fail? In Ethernet project as 3 clock we used in clocking wizard i.e clock_out1(166.667), clock_out2(200 MHZ ) and clock_out3(25 MHZ  ) why we use 166.667/200 MHZ frequency and 25 MHZ  clock_out3 is not connected to any port , why we required  clock_out3?

By hit and trail method reducing clock1 to 100 MHZ  

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Hi @neha,

I have not used the flash like this. I do not know if you can use the flash in this way. My understanding is that we used the 166.667 instead of 100 MHZ for clock 1 and 200 MHZ for clock 2 in the block design for the getting started with microblaze servers  and in the getting started with microblaze for the Arty-A7-35T to meet timing with the mig. The 25 MHZ clk is connected to the ethernet ref clock using the xdc to constrain the pin with the following:  set_property -dict { PACKAGE_PIN G18    IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #         Sch=eth_ref_clk .

thank you,

Jon

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@jpeyron

Greeting and thank you

I mean to say that instead of 166.667 MHZ we can use 100 MHz  too na as i used in my project using flash and  eth_ref_clock  why 25 MHz ? can We use other frequency too as 50Mhz etc. i change 166.667  to 100 Mhz because I am getting timing fail and clock was going to negative slack ,by doing that it  is remove. I mean to ask significance of 25Mhz and 166.667 MHz.
Actually in my project i able to  generate bitsteram  but its size 35 kb and bram size 32bit so while sdk lunch its keep coming not enough space in bram ,I tried to change  bit to 64 but thing is that read n write bit doesnot change from 8196  and then mismatch in address bus

 

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Hi @neha,

I'm not certain on the other clocks, but the 25 MHz clock is generated for X1 on the external PHY because that is what is required for the TI DP83848J as per it's datasheet, as detailed in section 4.5 on page 7 to operate in MII mode rather than reduced MII mode.

Thanks,
JColvin

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Hi @neha,

You can use an 100 MHZ clock for everything but the mig. Create an out put clock at 166.667 and have it connected to the sys_clk_i on the mig. We have some design that do this like the pmod wifi project.  I would suggest starting fresh with a new project with the larger microblaze memory setting initially to ensure everything build correctly. 

thank you,

Jon

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@jpeyron

Greeting and thank you

I start with microblaze  128kb/64 kb and 64kb/32kb local memory and cache configuration respectively. After compressing data and then generating bitstream in 128kb memory is coming 5.7kb and then launching sdk elf file is unable to generate and overflow of data as shown in picture elf_prb and  while is using  64 kb option  not enough memory option is showing.

Its look like dead end no idea where to go :(  i am using method https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start as mention in this and without this too(i.e dierct creating echo_server file)

But one thing above site mentioned step in spi_server link i unable get any right click option as shown in that doc selet "hello world" and  right click to generate  linker file   so  i was clicking on finish and get that error.

please help me. :(  and  is there any may to implement echo_server with out ddr3

elf prb.png

Edited by neha

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@jpeyron

Greeting

 thank you  for reply ,I will check for other option .

But i have one doubt, as I am following this link https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start .I notice that with  or without srec_spi_bootloader  ".elf file error is coming same ".

As in following link we have to change few thing in srec_spi_bootloader  in .h (flash image base address ) .c (comment verbose) saving the change , run again c file/ build all doesnot remove  warning in .h and .c file.

I am not sure But may be because srec_spi_bootloader is not generating  correctly that why error is coming !

Wospi.png

wspi.png

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I updated my echo_server in vivado 2018.2 version , while launching SDK in in bsp file error is coming:- " not to declared xemacap" in xadapter.c file
 

e_s.png

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