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qd0090

ddr2 spartan6 in ATLYS

Question

hi , i want to use ddr2 in ATLYS, though MIG in spartan6, i tried many days but it still do not work.

1. is there any reference design  for ATLYS about how to use ddr2? not in microblaze, just in ise, using vhdl or verilog

2. i upload my design files(because the project is larger than 0.49MB),  maybe someone can help me

i use ise 14.7,  now i am stuck in that the "c3_p0_wr_full" signal of the MIG ip never go low

thanks!

V3_DDR2_MT46H64M16.ucf

V3_DDR2_MT46H64M16.v

ddr2_atlys.v

infrastructure.v

memc_wrapper.v

mcb_controller.rar

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4 answers to this question

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Hello,

I have asked some of our applications engineers about this; they will get back to you here on the Forum.

Thanks,
JColvin

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I have followed the link @sLowe shared but it has some errors in it ( reset will never be deasserted because it relies on c3_clk0, which is never generated because the PLL is held in reset. Change line 64 of atlys_ddr_test.v to reg reset = 0; and design a proper reset controller ). 

Can someone please share a working reference design or a tutorial to be followed to interface Atlys Spartan 6 DDR2 using ISE. Thank you.  

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Hi @Hassan Iqbal,

Like slowe I have no experience with the mig for spartan 6 devices. That being said Here is the Spartan-6 FPGA Memory Controller user guide. Here is a thread from the xilinx forums that looks to be somewhat helpful. Here is a link to our resources page for the Atlys which has the flash memory config demo. The demo has code for the ddr2 as well as the flash. The resource page has many other demos for the atlys as well. Here is a link to the VmodCAM the has demos using the VmodCAM and the Atlys that might be helpful as well. 

cheers,

Jon

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