I’m planning to connect two Arty boards via a differential serial (SPI-like) interface to evaluate high-speed differential communication between the two FPGAs.
As far as I understand, I have to develop a pmod connection board with 50 Ω pull-up resistors on the TMDS_33 inputs, correct?
And (last question) is it possible to introduce a capacitive coupling between the 3.3 V outputs of the pmod headers as they are already connected via the 50 Ω pull-ups?
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Jammin
I’m planning to connect two Arty boards via a differential serial (SPI-like) interface to evaluate high-speed differential communication between the two FPGAs.
I thought about using the high-speed pmod connectors and the TMDS_33 IOSTANDARD as suggested in this https://forum.digilentinc.com/topic/1728-arty-selectable-25v-io-banks-for-lvds/ discussion.
Is this feasible?
As far as I understand, I have to develop a pmod connection board with 50 Ω pull-up resistors on the TMDS_33 inputs, correct?
And (last question) is it possible to introduce a capacitive coupling between the 3.3 V outputs of the pmod headers as they are already connected via the 50 Ω pull-ups?
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