After trying about everything I could think of, I am still not able to produce any sound through the DAC on the Zybo's audio chip.
I tried initializing the chip via I2C using what I think are the proper register values and the proper power on sequence, both using a core I wrote myself, and alternatively by connecting the I2C interface through to the Processing System and using Linux and i2c-tools there to set the register values from the command line. My initialization sequence includes activating the digital core (R9), enabling the DAC by setting DACSEL, unmuting the DAC, powering on both before (without Out) and after (with Out) setting the other registers and with the proper delay, and many more things. I am also pulling the active-low MUTE pin high using "i2c_m_mute <= '1';" in VHDL.
I can make the chip pop and hiss by powering it on, and I think I can manage to put Line In or Mic onto the output with the right register values (not entirely sure since I had no Mic laying around, but I'm relatively sure I heard something when I improvised with some ear buds). Overall, there's strong indication that my initialization sequence is at least partially successful, but the DAC remains entirely silent.
For the I2S signals, I have a 12.288MHz MCLK fed by a Clock Wizard, a 48kHz PBLRC clock, a 3.072MHz BCLK (for 64 cycles per 48kHz sample, but I also tried using half of that since I am only trying to feed 16bit data) and PBDAT aligned to that. I verified both with an ILA core and with an oscilloscope directly at the chip pins that the signals are there and look sound.
Yet I cannot even make the chip produce anything digitally. Even if PBDAT is screwed up, it should at least produce some sort of random noise or clicking, no?
What am I missing? Since I'm very new at FPGAs, this may be something entirely obvious.
Attached is an example of what is going on on the I2S wires. I tried at least left justification and the I2S format. This is with a BCLK for 32 bits per sample (i.e. 16bit per channel), as mentioned above I also tried using a 64bit BCLK with no effect.
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bajelly
After trying about everything I could think of, I am still not able to produce any sound through the DAC on the Zybo's audio chip.
I tried initializing the chip via I2C using what I think are the proper register values and the proper power on sequence, both using a core I wrote myself, and alternatively by connecting the I2C interface through to the Processing System and using Linux and i2c-tools there to set the register values from the command line. My initialization sequence includes activating the digital core (R9), enabling the DAC by setting DACSEL, unmuting the DAC, powering on both before (without Out) and after (with Out) setting the other registers and with the proper delay, and many more things. I am also pulling the active-low MUTE pin high using "i2c_m_mute <= '1';" in VHDL.
I can make the chip pop and hiss by powering it on, and I think I can manage to put Line In or Mic onto the output with the right register values (not entirely sure since I had no Mic laying around, but I'm relatively sure I heard something when I improvised with some ear buds). Overall, there's strong indication that my initialization sequence is at least partially successful, but the DAC remains entirely silent.
For the I2S signals, I have a 12.288MHz MCLK fed by a Clock Wizard, a 48kHz PBLRC clock, a 3.072MHz BCLK (for 64 cycles per 48kHz sample, but I also tried using half of that since I am only trying to feed 16bit data) and PBDAT aligned to that. I verified both with an ILA core and with an oscilloscope directly at the chip pins that the signals are there and look sound.
Yet I cannot even make the chip produce anything digitally. Even if PBDAT is screwed up, it should at least produce some sort of random noise or clicking, no?
What am I missing? Since I'm very new at FPGAs, this may be something entirely obvious.
Attached is an example of what is going on on the I2S wires. I tried at least left justification and the I2S format. This is with a BCLK for 32 bits per sample (i.e. 16bit per channel), as mentioned above I also tried using a 64bit BCLK with no effect.
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