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dakefeng

Petalinux on genesys2

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We don't have any petalinux BSPs for microblaze. Maybe one day, but not currently...

The easiest approach to jumping into petalinux will be to export your hardware from your Vivado project and import the .hdf file into a new petalinux project. I'm not going to get into detail too much here about how to do this, mainly because Xilinx already does a really good job of documenting it in their Petalinux Reference Guides (UG1144). Refer to that document for the petalinux version you are using for some in depth tutorials on how to do various tasks.

As for how to create a Petalinux BSP, you can skip that. Creating BSP files are really just a mechanism for archiving petalinux projects, so it is really only necessary if you need to distribute petalinux projects (like we do).

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Hello,

I have run into problems when trying to package the Petalinux image. I am using my own Genesys2 project with Microblaze configured for Linux MMU, interrupts, etc. as recommended in UG1144, p18. I can build the kernel apparently without error.

Both Iwan's page, and UG1144, show the following command without arguments. However I get an error when running it:

petalinux-package --boot --fpga images/linux/system_wrapper.bit --u-boot --kernel
ERROR: offset of bitstream "[your directory]/download.bit" is not specified.

There is a Xilinx forum post that recommends explicitly defining the packaging arguments (https://forums.xilinx.com/t5/Embedded-Linux/Petalinux-package-creating-download-bit-file/m-p/691113/highlight/false#M15793). However it's not specific to Genesys2. So I changed the flash device argument, and end up with something like this:

petalinux-package --boot --fpga images/linux/system_wrapper.bit --offset 0x000000 --fsbl images/linux/fs-boot.elf --u-boot images/linux/u-boot.elf --offset 0x800000 --kernel images/linux/image.elf --offset 0xa00000 --flash-size 256 --flash-intf SPIx1

Which generated the following message:
ERROR: [Writecfgmem 68-3] Bitstream at address 0x00800000 conflicts with bitstream at address 0x00000000.

I am guessing that the problem is the offsets specified. I cannot find any documentation in UG1144, UG1156, or UG1157 about where these offsets come from.

Has anyone gotten the package command to work? Is there another way to do it?

Thanks.

 

 

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I've had very little experience with microblaze and petalinux, but I documented the way I got it to work on our Arty S7 board here (I used Petalinux 2017.2):

https://github.com/Digilent/Petalinux-Arty-S7-50#arty-s7-50-petalinux-bsp-project

It looks like I used the following petalinux-package command:

petalinux-package --boot --force --fpga download.bit --fsbl none --u-boot --kernel --flash-size 16 --flash-intf SPIx4

Reading my notes on the linked site above, it looks like I wasn't able to get the Petalinux tools to generate a download.bit file properly. I chopped it up to the tools having limited support for the Spartan 7, but the problem could be endemic to all devices and I just couldn't figure out how to get the feature to work correctly. Either way, you can try my work around, which was to generate download.bit in SDK separately using the .bit and fs-boot.elf. 

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Thanks for the information about Petalinux tools not generating download.bit correctly.

I couldn't find an updated post about combining .bit and .elf using SDK. But I'm guessing that download.bit is supposed to be created when you go to "Program FPGA" in SDK 2017.2, then specify the .bit, .bmm, and fs-boot.elf files? I get an error message when I do that (and download.bit does not get created anywhere in the .sdk directory):

ERROR:Data2MEM:59 - Expected a 'tag' or 'tag' keyword in -bd option. Instead, encountered '/'.

It seemed that the SDK was not formatting the command syntax correctly (?). So I tried doing this manually:
data2mem -bm [my_proj].runs/impl_1/design_1_wrapper_bd.bmm -bt [my_proj].runs/impl_1/design_1_wrapper.bit -bd "[local_dir]/images/linux/fs-boot.elf" -o b [path_to_new_download_bitfile]/download.bit

When I download this to the Genesys2 board over JTAG, I get the following message at the serial console, which seems to indicate that this download.bit has the FPGA bitstream and the first stage bootloader! (However, I don't know why it warns me about the flash not being configured):

FS-BOOT First Stage Bootloader (c) 2013-2014 Xilinx Inc.
Build date: Dec  1 2017 10:59:46  
Serial console: Uartlite
FS-BOOT: FLASH is not configured.
FS-BOOT: Please download the image with JTAG.

Now I go back to sbobrowicz's petalinux-package command from above. I wind up with the same problem as before - it warns me that I didn't specify an offset. So this time I picked offsets based on the filesizes of download.bit and u-boot.elf:

petalinux-package --boot --format MCS --force --fpga [path_to_new_download_bitfile]/download.bit --offset 0x000000 --fsbl none --u-boot images/linux/u-boot.elf --offset 0xAE9E0E --kernel images/linux/image.elf --offset 0xC94F53 --flash-size 32 --flash-intf SPIx1 --output genesys.mcs

which generates an .mcs file.

Now when I try to program the S25FL256xxxxxx0 part through Vivado, it gets through the erase process, but then the board always disconnects itself before the programming is finished.

 

So I don't know if the .mcs programming file I'm creating is valid. (I can boot the kernel in QEMU, and I can boot U-boot over JTAG, so I think the individual components are all okay, and I'm not understanding something about how to glue it together). Is there a way to verify it?

Why does this process differ so much from the documentation (others seems to be able to get the petalinux-package command to work with minimal arguments)? I am using Petalinux 2017.2, Vivado 2017.2, and SDK 2017.2.

 

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