Maximum flash speed

[D@n]

Greetings!

I just purchased my first Arty, and I'm now preparing for the board to arrive.

One of my goals with the Arty board will be to see how fast I can clock things both internally and externally.  As examples, I'm hoping to clock a custom CPU (the ZIpCPU) at 200MHz, to build a custom memory interface that will clock at 200MHz, and ... a flash controller at 200MHz that will generate a 100MHz flash clock.

While preparing for this project, I noticed that the web page reference manual for the Arty states that the QuadSPI flash has a maximum clock rate of 50MHz.  The data sheet that I managed to find online, though, suggests that the same flash may be clocked instead at up to 108MHz. 

Can you tell me if the 50MHz rate listed on the reference manual page for the Arty is a typo that should really read 108MHz, or if there is some other reason the flash clock is limited to 50MHz?

Thanks,

Dan

P.S.  If anyone is interested in this project and its progress, let me know.  If you'd like, I could even open up a project and/or blog at OpenCores for it ...  Either way, I intend to share things in the Project Vault once they work.

[JColvin]

Hi Dan,

I have asked some of our applications engineers to see what the reasoning is for the listed 50 MHz spec; they will get back to you here on the forum.

Thanks,
JColvin

 

[mskreen]

Hello D@n,

 

So after a little research into the QuadSPI clocking speeds on the Arty I think I have some useful information to help solve your question. In Xilinx's Using SPI Flash with 7 Series FPGAs, page 9 talks about the SPI flash configuration clocks that can be used on the 7 series FPGAs. The documentation notes that the max SPI flash clock frequency for a  Kintex-7 XC7K325T FPGA is ~93.897 MHz and that internal oscillators suffer from a +/-50% frequency tolerance. So if the internal oscillator is being used to clock the QuadSPI flash it is recommended to use a clock of 50MHz so that at the fastest (50MHz * 1.5 = 75MHz) clock speed is well under the maximum SPI flash clock and therefore shouldn't encounter any clocking related issues. This is the reason for why the reference manual states a max SPI flash clock of 50 MHz. That being said, if you have an external clock of say 80MHz, you would be able to use that to clock your SPI flash. Increasing the speed of the internal oscillator may work, so you might be able to test out a speed of 100MHz, but you will most likely run into some problems. I hope this helps some.

 

Respectfully,

Mikel

[D@n]

Mike,

Thanks for the prompt answer!  Looking at the data sheet for the Artix-7 SPI, specifically the "Micron Serial NOR Flash Memory: N25Q128A" data sheet, it defines a "clock LOW to output valid under 30pF" as 7ns, and a "clock LOW to output valid under 10pF" as 5ns (p72).  Further, the data sheet for the Artix-7 lists the setup time, when using an MMCM clock, to be 3.35ns (p44-if I have the right table)--a touch slower than the Kintex.  Put together, this should yield a maximum clock frequency of between 1/(5ns+3.35ns)=119MHz and 1/(7ns+3.35ns)=96MHz depending upon whether the capacitance is 10pF or 30pF.  Do you know how or where I might find this capacitance number?

Dan

[mskreen]

So I just spoke with one of our engineers and it turns out that the Arty's QuadSPI was never thoroughly tested past 50 MHz. It was concluded that if you are using the QuadSPI to configure the FPGA then it is recommended to not surpass 50 MHz, but if you are using it as an active memory at run time for your project then it is most likely possible to reach speeds closer to 100 MHz. I apologize but the capacitance of the lines are not known to me and I do not have the tools to measure them. Of course you are free to test the bounds of your board and I am interested to hear about your findings.

Best of luck,

Mikel

[D@n]

Mike,

Thank you for the encouragement!  I think I will do just that: I'll test the bounds of how fast I can get a controller to go, and post the results back when I have them.  My goal will be to get it up to 100MHz, and I'll let you know how close I get.

But, yes, like you said, one of my motivations is to use the SPI as an active ROM memory for my project and, when doing that, the faster it goes the faster everything else can go when using it.

Who knows, perhaps you'll want the HDL I put together so that you can test your next board and see if the SPI can be made to run at 100MHz?

Yours,

Dan

[D@n]

FYI,

Looks like I'm getting a lot closer.  My new controller works at 100MHz, just not 200MHz.  I think I've traced the problem down to the STARTUPE2 primitive that I'm still using.  The artix-7 data sheet notes that the time delay between user input and the output can be anything between 0.5ns (possibly doable) and 7.5ns (absolutely impossible).  So I'm rebuilding now without the STARTUPE2 primitive (which is possible on the Arty--thanks Digilent for including pin L16 to the flash clock!).  I'm also switching to DDR primitives, to make sure I have the port timing cleaned up properly.

I'll keep you posted.

Dan

[D@n]

Okay, looks like it works at 200MHz--in Quad Output mode.  The DDR primitives were a non-starter, but delaying the read by one clock was enough to make it work.  Well, that and getting off of the CCLK pin via the STARTUPE2 primitive.  I still need to test XIP and writing, but it's close enough I'm convinced it can be done.

I'll keep my work posted here (with the entire project here).

Dan