I am trying to transfer the status of my I/O pins via UART on nexys 3 . While I am sending it only one time no error occurs but if I send it in a loop it shows error.

[devchandil]

The code is as follows: 

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity uartwithclk is
PORT(
CLOCK_50 : in std_logic;
SW : in std_logic_vector(9 downto 0);
KEY : in std_logic_vector(3 downto 0);
UART_T : out std_logic;
CLK_OUT : inout  STD_LOGIC;
RESET : in  STD_LOGIC
);
end uartwithclk;

architecture Behavioral of uartwithclk is
SIGNAL COUNT : INTEGER:=0;
SIGNAL TEMP : STD_LOGIC:='0';
SIGNAL TX_DATA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL TX_START: STD_LOGIC:='0';
SIGNAL TX_BUSY: STD_LOGIC;
COMPONENT com
PORT(
           CLK : in  STD_LOGIC;
           START : in  STD_LOGIC;
           BUSY : out  STD_LOGIC;
           DATA : in  STD_LOGIC_VECTOR (7 downto 0);
           TX_LINE : out  STD_LOGIC
);
END COMPONENT com;
TYPE t_2KB IS ARRAY (0 TO 2047) OF std_logic_vector (7 DOWNTO 0);
SIGNAL mem : t_2KB;
begin
C1 : com PORT MAP(CLK_OUT,TX_START,TX_BUSY,TX_DATA,UART_T);
PROCESS(CLOCK_50,RESET)
VARIABLE I : integer range 0 to 2000;

BEGIN 

IF RESET='1' THEN
COUNT<=0;
TEMP<='0';
ELSIF RISING_EDGE(CLOCK_50) THEN
COUNT<=COUNT+1;
IF COUNT=1 THEN
TEMP<=NOT TEMP;
COUNT<=0;
END IF;
END IF;
CLK_OUT<=TEMP;

I:=0;
while(I<=1998) loop
IF(CLK_OUT'EVENT AND CLK_OUT='1') THEN     -- Error occus here "statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition"
IF(KEY(0)='1' AND TX_BUSY='0') THEN
TX_DATA<=SW(7 DOWNTO 0);
TX_START<='1';
ELSE
TX_START<='0';
END IF;
END IF;
I:=I+1;
end loop;

END PROCESS;
end Behavioral;
 

 

com code:

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

 

entity com is
    Port ( CLK : in  STD_LOGIC;
           START : in  STD_LOGIC;
           BUSY : out  STD_LOGIC;
           DATA : in  STD_LOGIC_VECTOR (7 downto 0);
           TX_LINE : out  STD_LOGIC);
end com;

architecture Behavioral of com is
SIGNAL PRSCL: INTEGER RANGE 0 to 5208:=0;
SIGNAL INDEX: INTEGER RANGE 0 to 9:=0;
SIGNAL DATAFLL: STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL TX_FLG: STD_LOGIC:='0';
begin
PROCESS(CLK)
begin
IF(CLK'EVENT AND CLK='1') THEN
   IF(TX_FLG='0' AND START = '1') THEN
    TX_FLG<='1';
    BUSY<='1';
    DATAFLL(0)<='0';
    DATAFLL(9)<='1';
    DATAFLL(8 downto 1)<=DATA;
    END IF;
    IF(TX_FLG='1') THEN
    IF(PRSCL<5207) THEN
    PRSCL<=PRSCL+1;
    ELSE
    PRSCL<=0;
    END IF;
    IF(PRSCL=2607) THEN
    TX_LINE<=DATAFLL(INDEX);
    IF(INDEX<9)THEN
    INDEX<=INDEX+1;
    ELSE
    TX_FLG<='0';
    BUSY<='0';
    INDEX<=0;
    END IF;
    END IF;
    END IF;
    END IF;
    
    END PROCESS;

end Behavioral;

[hamster]

Hi,

Your problem is that you can (in general) only have one test for a clock signal in a process. 

You are after a structure more like:

process(reset, your_clock)
begin
  if reset = '1' then
     loop_counter <= to_unsigned(0,10);
  elsif rising_edge(your_clock) then
    if loop_counter < to_unsigned(999,10) then
       .... do something once...
       loop_counter <= loop_counter+1;
    else
      .... what to do once finished ...
    end if;
  end if;
end process

That will result in something happening 1000 times, each time reset signal is released.