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JColvin

Running Vivado from the command line

Question

A customer on our website asked the following question:

I plugged in the Arty-board, and things twinkled, and I was VERY PLEASED that
the Digilent/adept/djtg API that I downloaded years ago and use with my various older
Digilent boards works with this new board too for jtag communication with the fpga.
So I should be able to use EXACTLY the SAME scheme for jtag-configuring
from .svf files that I use with the older boards. Great!

3. But, sadly, it seems I have to use Vivado, not ISE, with this board. Is there really no
way to use ISE??? If not, then I shall use vivado, like ISE, from a script (gnu/linux), not from the GUI.
So do you have an example of a single command-line that takes a .vhd, and a .ucf and
causes Vivado to produce a .svf? Without any GUI clicking, and without me having to
spent a lot of time (as I did with ISE) to find out how to do this??? I am sure I am not the first to ask.

Thanks in advance

The response is below.

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Hello,

I have asked some of our applications engineers about this since I am personally unfamiliar with doing anything like that. 

Thanks,
JColvin

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I almost always run Vivado in scripted mode. It's so much more convenient that way. And Vivado is so much better than ISE.

I use Vivado in GUI mode to add or use the integrated logic analyzer. It is possible to instantiate integrated logic analyzers from scripts, but the GUI is required to use it.Here is a simple script that should do what is requested:

create_project $module -in_memory -part $partname
add_files file.vhd
read_xdc file.xdc
synth_design -name $module -top $module -part $partname
write_checkpoint -force $module-synth.dcp
link_design
opt_design
place_design
write_checkpoint -force $module-place.dcp
phys_opt_design
route_design
write_checkpoint -force $module-routed.dcp
report_timing_summary
write_bitstream $module.bit

 

 

Caveat: I have not tested this particular script and I do not write vhdl. I usually run synthesis and implementation with separate invocations of vivado because I use a hierarchical flow, synthesizing multiple netlists per design. The scripts I use are in fpgamake: https://github.com/cambridgehackers/fpgamake/blob/master/tcl/synth.tcl and https://github.com/cambridgehackers/fpgamake/blob/master/tcl/topdown.tcl which are synthesis and implementation scripts that are more comprehensive.

The VIvado tcl commands documentation is pretty good: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug835-vivado-tcl-commands.pdf

 

Edited by jamey.hicks
clarification

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