Are pairs of Eclypse Z7 ZMOD single ended pins routed differentially?

[GlenW]

I would like to use some of the single-ended pins on the ZMOD connectors as differential pairs even though the SYZYGY spec does not state this is legal.  I only care to use the PCB we are designing with the Eclypse Z7.  The pins go to differential pins on the FPGA so it is completely possible if they are routed properly.

For instance SYZYGY_A_S21 and SYZYGY_A_S23 got to IO_L8N_T1 and IO_L8P_T1 on the FPGA and pins 26 and 28 on the SYZYGY connector which are fine for a differential pair.

Thanks

Glen

[zygot]

I'd be surprised if the single-ended signals for the Eclypse-Z7 ZMOD ports are "laid out as differential" based on other boards that they've done. There's more to high speed PCB trace routing than just trace dimensions and relative spacing.

Start another post asking for someone at Digilent to provide the trace length report for Eclypse-Z7 ZMOD signals. I doubt that Digilent wants to publish Gerber files.

Make sure that you understand the SYZYGY DNA process and how it's implemented on the carrier board that you want to connect your add-on board to. Go to Opal Kelly's web site to get the pertinent SYZYGY standard documentation.

Edited January 13, 2022 by zygot

[zygot]

My understanding of your question is that you want to design your own SYZYGY pod but don't want to follow the SYZYGY specification.

There's no law against using a particular connector anyway that you want to. There's no law against violating an interface specification to implement an add-on board. There certainly are potential problems when converting single-ended signals to differential signals.

1.  It's unlikely that the single-ended signals on the Eclypse-Z7 routed to the ZMOD ports are suitably length matched. This is the most important, though not necessarily the only criteria, for differential signalling.
2. You are limiting your add-on board to be used with only one FPGA carrier board, and possibly only one of the ZMOD ports.
3. If the Eclypse-Z7 is receiving your differential signal you will not be able to have optima placement of the differential termination. in this scenario you could, possibly, counter length matching using IDELAY. There is no ODELAY for Z7020 PL pins.

If may be that none of the above considerations matter to your application. It depends on the application and performance.  Just make sure that any single-ended signals are on the correct IO banks for the ZMOD Vadj supply control. And make sure that you don't confuse your add-on card with a SYZYGY pod.

Differential signalling, if it includes differential drivers and differential receivers, and has _n and_p PCB traces length matched and the traces are laid out following differential signalling rules ( there's more than one way to do this ) offer superior common mode noise rejection and is less susceptible to what's going on around them. Differential signalling also offers balanced current sourcing and sinking and reduces ground reference and ground bounce issues. The quality of differential signalling starts being degraded when you don't follow the rules carefully. This isn't always a problem.. if you do your analysis properly. It depends on your application specifications.

 

[GlenW]

zygot, thanks for the response.  I understand the issues.  What I would really like is some gerber files so I can see how these signals are routed.  I believe it is possible the signals were routed as if they were differential.