Trying to expand the number of GPIO ports on the Zybo Z720, the method which I am currently using is assigning PMOD port JE as the IO ports by changing the constraint files in vivado, however not successful in initializing and reading/writing those pins.

[ilovefpga]

I followed this forum and changed the constraint files of the Zybo Z720 in Vivado and successfully generate bitstream and the xsa file to import into Vitis. https://forum.digilentinc.com/topic/8943-pmod-as-input-and-output-gpio/

#Pmod Header JE                                                          

set_property -dict { PACKAGE_PIN V12  IOSTANDARD LVCMOS33 } [get_ports { je_pin1_io }];  

set_property -dict { PACKAGE_PIN W16  IOSTANDARD LVCMOS33 } [get_ports { je_pin2_io }];           

set_property -dict { PACKAGE_PIN J15  IOSTANDARD LVCMOS33 } [get_ports { je_pin3_io }];            

set_property -dict { PACKAGE_PIN H15  IOSTANDARD LVCMOS33 } [get_ports { je_pin4_io }];          

set_property -dict { PACKAGE_PIN V13  IOSTANDARD LVCMOS33 } [get_ports { je_pin7_io }];      

set_property -dict { PACKAGE_PIN U17  IOSTANDARD LVCMOS33 } [get_ports { je_pin8_io }];       

set_property -dict { PACKAGE_PIN T17  IOSTANDARD LVCMOS33 } [get_ports { je_pin9_io }];         

set_property -dict { PACKAGE_PIN Y17  IOSTANDARD LVCMOS33 } [get_ports { je_pin10_io }];   

I am able to control the GPIO pins of port JF on the Zybo Z720 using the following code, how do I edit this so that I am able to turn on/off LEDs using the Pmod port JE instead.

#include "xil_cache.h"

#include "xparameters.h"

#include "stdio.h"

#include "xparameters.h"

#include "xuartps.h"

#include "xtime_l.h"

#include "xgpiops.h"

#include "sleep.h"

#include "xil_io.h"

#include "xil_types.h"

#include "xil_printf.h"

#include "sleep.h"

#include "stdlib.h"

#include "string.h"

 

#define HOST_UART_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID

#define HostUart XUartPs

#define HostUart_Config XUartPs_Config

#define HostUart_CfgInitialize XUartPs_CfgInitialize

#define HostUart_LookupConfig XUartPs_LookupConfig

#define HostUart_Recv XUartPs_Recv

#define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->BaseAddress)

#define PMODESP32_UART_BASEADDR XPAR_PMODESP32_0_AXI_LITE_UART_BASEADDR

#define PMODESP32_GPIO_BASEADDR XPAR_PMODESP32_0_AXI_LITE_GPIO_BASEADDR

#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)

#define TIMER_FREQ_HZ 100000000

#define MAX_WIDTH 320

#define MAX_HEIGHT 240

#define MAX_BUTTON 16

 

#ifdef __MICROBLAZE__

#define HOST_UART_DEVICE_ID XPAR_AXI_UARTLITE_0_BASEADDR

#define HostUart XUartLite

#define HostUart_Config XUartLite_Config

#define HostUart_CfgInitialize XUartLite_CfgInitialize

#define HostUart_LookupConfig XUartLite_LookupConfig

#define HostUart_Recv XUartLite_Recv

#define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->RegBaseAddr)

#include "xuartlite.h"

#include "xil_cache.h"

#else

#define HOST_UART_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID

#define HostUart XUartPs

#define HostUart_Config XUartPs_Config

#define HostUart_CfgInitialize XUartPs_CfgInitialize

#define HostUart_LookupConfig XUartPs_LookupConfig

#define HostUart_Recv XUartPs_Recv

#define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->BaseAddress)

#include "xuartps.h"

#endif

 

#define PMODESP32_UART_BASEADDR XPAR_PMODESP32_0_AXI_LITE_UART_BASEADDR

#define PMODESP32_GPIO_BASEADDR XPAR_PMODESP32_0_AXI_LITE_GPIO_BASEADDR

#define BLOCK_SIZE 40

 

void startup();

 

XGpioPs_Config *ConfigPtr;

XGpioPs output;

 

int main() {

  startup();

  while(1)

  {

  XGpioPs_WritePin(&output, 13, 1); //led on (pin 1,2,3,4)

  XGpioPs_WritePin(&output, 10, 1);

  XGpioPs_WritePin(&output, 11, 1);

  XGpioPs_WritePin(&output, 12, 1);

}

 

  void startup(){ //initialize pins for JF

 

  ConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);

  XGpioPs_CfgInitialize(&output, ConfigPtr, ConfigPtr->BaseAddr);

 

  XGpioPs_SetDirectionPin(&output, 13, 1);

  XGpioPs_SetOutputEnablePin(&output, 13,1); //pin1 JF1

 

  XGpioPs_SetDirectionPin(&output, 10, 1);

  XGpioPs_SetOutputEnablePin(&output, 10,1); //pin2 JF2

 

  XGpioPs_SetDirectionPin(&output, 11, 1);

  XGpioPs_SetOutputEnablePin(&output, 11,1); //pin3 JF3

 

  XGpioPs_SetDirectionPin(&output, 12, 1);

  XGpioPs_SetOutputEnablePin(&output, 12,1); //pin4 JF4

}

[artvvb]

Hi @ilovefpga,

Pmod port JF is connected to the Zynq PS and is controlled via the xgpiops driver, as you have seen. The other Pmod ports are all connected to the Zynq PL and need to be controlled through the FPGA fabric and constrained in an xdc, as you have seen. If you use an AXI GPIO or Pmod GPIO IP core (as seen in the thread you linked), you need to use the xgpio drivers (written for the PL IP) instead of the xgpiops drivers. Alternatively, you could configure the Zynq PS to provide an 8-bit GPIO EMIO interface, make that interface external, and constrain it in the xdc. The EMIO option would use the xgpiops drivers and likely reuse most of the same code you already have (changing some of the hardcoded pin numbers). A starting point for configuring the Zynq block for this can be seen in the attached screenshot.

Could you provide a screenshot of your block diagram?

Thanks,

Arthur