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JTAG-SMT3 to MachX02


Question

Hello all,

I am facing a strange issue.

I am using a JTAG-SMT3 probe on my product to program the following components:

image.png.0da8c547dae05bbb54d6890b671115ea.png

On the first prototypes all was working fine:

- I am able to program Xilinx FPGAs with Vivado

- I am able to program Lattice MachXO2 with diamond programmer

On the second batch, I am always able to program with Vivado but unable to do a simple boundary Scan with diamond.

I've replaced the JTAG-SMT3 by a Trenz TE0790 on one board and it is working fine with diamond programmer.

The JTAG-SMT3 probes don't come from the same command/batch on the 2 versions of our board. The one with a green quality check sticker on the FTDI are not working properly. There is no sticker on the first prototypes.

I've not found in the JTAG-SMT3 documentation a point related to different version of this probe? Have this probe different version ? Have you an idea of what's happen?

Thanks for your help

Marc

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Hi @Quemar,

I am not aware of any changes to the JTAG SMT3 though I will double check this.

Is the same version of the Vivado / diamond programmer / general operating system being used between the two versions of the board (in the interest of ruling out software causing issues, like Vivado's hw_server attempting to maintain access on the device).

Also to clarify, with the replacement of the JTAG SMT3 with the Trenz TE0790, are you still able to successfully program the Xilinx based FPGAs/SoC's and switch back and forth between them and the Lattice board?

Thanks,
JColvin

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Hi @Quemar,

I read the PM you had sent me before; to clarify the FTDI markings on the FTDI chip are just the date and manufacturing lot not number that FTDI places on their chips as explained in Section 9.6 of their datasheet: https://ftdichip.com/wp-content/uploads/2020/08/DS_FT232R.pdf.

I also got confirmation that there has been no change to the JTAG SMT3 since it's creation in 2017.

Unfortunately though, Digilent has not worked with Lattice boards or the Diamond Programmer, so I am uncertain as to why the boundary scan is not successfully completing. If it's an option, I would probably try lowering the JTAG clock speed to see if the boundary scan is successful.

Thanks,
JColvin

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Hi @JColvin,

Thanks for your feedback.

I've already done lots of your advices last week:

- We tested with many version of Vivado HWdebugger and Diamond programmer and it was always the same result. Always ok with Xilinx and not with Diamond

- We are always able to access all the chain with Vivavo whatever if the Lattice is programmed or not or if we previously used diamond or not.

 - We tried with different clock speed and this has no impact (always the same result with Vivado and Diamond)

- We have probed all the JTAG signals and we think there are "electrically good"

Our conclusion is that there is a timing problem due to the use of different buffers on the Digilent probe that causes bad timing with Diamond.

That can be due to a batch of components which are limit. 

We continue to investigate but if someone has a best explanation?

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Hi @JColvin,

The main conclusion of all this problems is that we can't integrate your JTAG-SMT3 probe in our design. We don't know why but it's like that...

We need to intergrade our self JTAG probe compatible with Xilinx and Lattice tools on our board.

For that, we will implement our own design based on a FTDI FT2232H and for that I think we need to buy a Xilinx-Digilent licence ?

Could you give me the procedure or the contact to discuss with to buy such licence ?

Thanks,

Marc

 

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Hi all,

We found the cause of our problem without understanding exactly the problem.

The problem comes from the level shifter on the TCLK which is not driven with diamond but is with Vivado.

The TCLK is correctly generated on FT2232H side, but does not pass through the level shifter. Maybe because OE for TCLK is not correctly driven? But Why?

And why with other JTAG-SMT3 the TCLK is working correctly?

Are you sure there is no different versions of the JTAG-SMT3?

Could you provide us the schematic and the layout, thus we could investigate? (Revert engineering on a small board like that is really time consuming !)

We need really to find a solution, and quickly, because this stops a very important production !

A quick reply would be strongly appreciated.

Thanks,

Marc.

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Hi @Quemar,

I asked one of design engineers about this and they assured me that there has not been any changes of any kind to the SMT3.

Would you be able to share more detail on how your two versions are set up in terms of the JTAG connectivity and where you measured the TCLK signal so our design engineer can see if anything jumps out at them?

Otherwise based on what you have described and considering that the SMT3 is the only programmer on your board (as I understand it) and the Vivado Hardware Manager is correctly driving the JTAG signals in both versions of your systems, this indicates to us that the Lattice software (Diamond programmer) is not driving the OE pin correctly, if indeed that is the problem at hand; maybe this could be because the Diamond programmer is expecting the OE pin to be in a certain stable state rather driving the pin, or maybe it is something unrelated entirely.

Thanks,
JColvin

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Hi @JColvin

We made the following measurements on the JTAG-SMT3 module which is on our board.

All the scope print screen are done with the following configuration:

In yellow: TCLK on the output of the JTAG-SMT3 module, pin 10. (After the LS buffer)

In blue: TCLK on the FTI FT2232H chip pin 16. (before the LS buffer)

In red: TMS on the output of the JTAG-SMT3 module, pin 13.

In green: DATA out on the output of the JTAG-SMT3 module, pin 12.

 

1. Measurement done with Xilinx Vivado debugger tool:

scope_21.png.3739da564dabd52c6f520585a17b8c93.png

All the signals are correctly driven and the JTAG chain is correctly detected.

 

2. Measurement done with Lattice Diamond programmer tool:

scope_22.png.8a4c253840737df0f0ca8759220873b6.png

The JTAG chain is not detected and we can see there is no correct TCLK output.

 

3. The last measurement is done with another external "good" JTAG-SMT3 connected in parallel of the JTAG-SMT3 module on our board. The JTAG-SMT3 on our board is not powered and is in high impedance.  Measurement done with Lattice Diamond programmer tool:

scope_23.png.cdc3c835a4c7be30a955b91759cd981f.png

The JTAG chain is correctly detected but we can see that the TCLK signal partially correctly driven driven.

Are you able to explain such differences ?

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Hi @Quemar,

We're not certain of why you are seeing the differences when using Diamond Programmer with the JTAG SMT3.

Out of curiosity though, what led you to believe that the Lattice Diamond Programmer tool would be compatible with the Digilent programmers? It does not appear to indicate on the download page for the Diamond Programmer, and this thread and reference page seem to indicate that Digilent based programmers solutions are not compatible with Lattice, nor does Digilent claim this.

Thanks,
JColvin

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Hi @JColvin,

Thanks, for your feedback. 

On our side we confirm than due to the output level shifter buffer on the TCLK of the JTAG-SMT3, this JTAG probe is not compatible with Lattice.

If we remove this buffer, the probe became compatible with Lattice.

On our first version of the board we had the luck or the unluck that it worked !

To go ahead, we are interested to implement the FTDI chip as a Digilent JTAG probe compatible with Xilinx.

As already asked in this tread, is it possible to buy a Digilent licence in order to design our own JTAG probe?

Thanks for your help.

Marc

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