CmodA7-35t - Vitis2021.2 - MicroBlaze and SREC Bootloader

[BYTEMAN]

Dear all,

testing with the latest release of Vivado and MicroBlaze with the CmodA7-35t board give a compilation error in Vitis (equivalent to the new SDK of the old Vivado release), the strange things is that same design can not be fit here the compilation error:

'Invoking: MicroBlaze gcc linker'
mb-gcc -Wl,-T -Wl,../src/lscript.ld -LC:/Users/........./Xworkspace/blinkymb_wrapper/export/blinkymb_wrapper/sw/blinkymb_wrapper/standalone_microblaze_0/bsplib/lib -mlittle-endian -mcpu=v11.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "blinkymb.elf"  ./src/bootloader.o ./src/platform.o ./src/srec.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
c:/xilinx/vitis/2021.2/gnu/microblaze/nt/x86_64-oesdk-mingw32/usr/bin/microblaze-xilinx-elf/../../libexec/microblaze-xilinx-elf/gcc/microblaze-xilinx-elf/10.2.0/real-ld.exe: blinkymb.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem'
c:/xilinx/vitis/2021.2/gnu/microblaze/nt/x86_64-oesdk-mingw32/usr/bin/microblaze-xilinx-elf/../../libexec/microblaze-xilinx-elf/gcc/microblaze-xilinx-elf/10.2.0/real-ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 8904 bytes

in bold the relevant part of the error message, I got an overflow error related the MicroBlaze memory occupation that is not enough (overflow of 8904 bytes), searching through the forum, from another thread, I can read this answer:

"basically you went out of space, your application does not fit into the provided BRAM memory. This is mostly because when you add the xil_printf function the implementation on the library of the printf needs some space too, when you do not use it it is optimized and removed by the linker. You need more memory on your device to fit all the drivers and BSP stuff (at least if you are using them)."

Then I've did a try avoiding the bootloader to be verbose, so into the bootloader.c source code I've commented the #define VERBOSE, the new compilation give again the memory error despite the overflow was reduced:

'Building target: blinkymb.elf'
'Invoking: MicroBlaze gcc linker'
mb-gcc -Wl,-T -Wl,../src/lscript.ld -LC:/Users/........../Xworkspace/blinkymb_wrapper/export/blinkymb_wrapper/sw/blinkymb_wrapper/standalone_microblaze_0/bsplib/lib -mlittle-endian -mcpu=v11.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "blinkymb.elf"  ./src/bootloader.o ./src/platform.o ./src/srec.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
c:/xilinx/vitis/2021.2/gnu/microblaze/nt/x86_64-oesdk-mingw32/usr/bin/microblaze-xilinx-elf/../../libexec/microblaze-xilinx-elf/gcc/microblaze-xilinx-elf/10.2.0/real-ld.exe: blinkymb.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem'
c:/xilinx/vitis/2021.2/gnu/microblaze/nt/x86_64-oesdk-mingw32/usr/bin/microblaze-xilinx-elf/../../libexec/microblaze-xilinx-elf/gcc/microblaze-xilinx-elf/10.2.0/real-ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 4032 bytes

the overflow was reduced to 4032, but still present.

Someone have encoutered similar issue in porting from old Vivado to the latest release? Some hint?

Thanks and best regards.

F.

UPDATE FOR SOLUTION

Dear all,

after some searching and test I was able to compile properly the bootloader inside Vitis.

To achieve this of course we have to enlarge the BRAM into design, but this can not be achieved directly from the Block Design by working around the MicroBlaze local memory IP, you have instead to work on the Address Editor tab, looks below the final settings to do:

because the message was related the program size, we have to work on the /microblaze_0/Instruction (then the memory space reserved for the program code, about data I've changed it to 32k and I think is enough) so I've incremented this value up to 64K (with 32k the memory space error was still present).

After did this change you have to run again the bitstream generation (if you do not launch from this you got the [Board 49-67] error when you try to generate the bitstream, this is a know issue from the past Vivado release, but I confirm that is still present also into the latest Vivado 2021.2, but if you run the synthesis and implementation directly from the bitstream, so in one single passage, this warnings is not show), after the bitstream generation, if you look at the Block Manager and double click into the MicroBlaze local memory as shown below:

and then double click inside the lmb_bram block responsible for the local block memory generation inside the FPGA, you will see now that the Write Depth is increased accordling to the setting did into the Address Editor window!

After exporting the Hardware and then launch Vitis the compilation of the SREC bottoloader was fine, here below the message at the end of the bootloader compilation:

...

'Building target: cmoda7qspi.elf'
'Invoking: MicroBlaze gcc linker'
mb-gcc -Wl,-T -Wl,../src/lscript.ld -LC:/Users/........../Xworkspace/design_1_wrapper/export/design_1_wrapper/sw/design_1_wrapper/standalone_microblaze_0/bsplib/lib -mlittle-endian -mcpu=v11.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "cmoda7qspi.elf"  ./src/bootloader.o ./src/platform.o ./src/srec.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group
'Finished building target: cmoda7qspi.elf'
' '
'Invoking: MicroBlaze Print Size'
mb-size cmoda7qspi.elf  |tee "cmoda7qspi.elf.size"
   text       data        bss        dec        hex    filename
  14636        316       2096      17048       4298    cmoda7qspi.elf
'Finished building: cmoda7qspi.elf.size'
' '

14:33:22 Build Finished (took 2s.853ms)

so the memory occupation overflow was not present! Yep!

Then the next step will be try to set up the classical "Hello World" application to test also the UART communication and put all into the SPI memory to have the program running at the power cycle.

PROPOSAL

Due to the Cmod A7-35t is a very nice evaluation board I kindly ask the Digilent team if is possible to update the oldest tutorial for the Cmod A7-35t and QSPI at the latest Vivado/Vitis release.

Thanks for your time!!

Byteman

Edited December 31, 2021 by BYTEMAN
SOLUTION

[BYTEMAN]

Dear all,

now the question is how to instruct the bootloader about the physical SPI flash that I'm using as we did into the previous release of Vivado by including the xilifs library that actually is deprecated and then no more available! Look at the image below:

Anyone have some idea?

Thanks!

 

[BYTEMAN]

Someone have some idea?

Thanks and best regards.

[BYTEMAN]

I've did some test by using the SREC SPI bootloader, despite the xilisf library is no more available I think that the driver should be able to work also as is provided into the new release (Vivado and Vitis 2021.2), now after doing all the classical step to make the composite bin file from the bitstream and the bootloader and then after program it into the SPI Flash and also after programming the application program into the SPI flash (of course the bootloader FLASH_IMAGE_BASEADDR was properly set with same value used into the flash programming for the application code), when I perform the power cycle to the Cmod A7-35t board nothing appear (the Hardware Manager in Vivado is closed), but by pressing the BTN0 (that should be connected to the reset input) I got this output:

someone have idea how to avoid such error?

Thanks!

[BYTEMAN]

Another little step, now all seems able to work but to do that I've to apply the change as reported inside this forum thread:

https://support.xilinx.com/s/question/0D52E00006hpafvSAA/issue-with-booting-from-qspi-flash-using-srec-spi-bootloader-for-microblaze?language=en_US

the part that solve this issue is on the last post, here below the detailed step with some image taken from Vivado.

In Vivado open the Block Design, I'm assuming you have the AXI Quad SPI IP core inside the design.

You need to re-customize the core.

double click inside the AXI Quad SPI block and check about the following options:

Under the IMPLEMENTATION tab inside the Flow Navigator select Open Implemented Design, then select Tools->Edit Device Properties... option, make sure that in Configuration under the SPI Configuration section, the  BUS width option is set to NONE.

select the Configuration Modes and check that your Configuration Mode is Master SPI x1.

Next you have to regenerate the bitstream so go into the Flow Navigator panel and under the PROGRAM AND DEBUG panel select Generate Bitstream.

Next go to File->Export->Export Hardware and after it finish you can create the new composite bitstream using the Associate ELF File and then Generate Memory Configuration File, from this point all the others step are same to the ones listed into the "How To Store Your SDK Project in SPI Flash" tutorial.

The composite bitstream can be written inside the SPI Flash serial memory by means of the Hardware Manager from Vivado:

looks for the composite bitstream and load it as Configuration file, choose the Memory Device and press OK to program the SPI memory on the Cmod A7-35t board.

The programmed bitstream have the FPGA fabric definitions and the bootloader code.

Now you have to go in Vitis and program the Application program by using the Xilinx->Program Flash option, choose the elf file of your application and make sure to write as Offset the one used into the blconfig.h (bootloader), for this board 0x00300000 is fine. You must also not forget to check the "Convert ELF file to bootable SREC format" because the bootloader is designed to manage the SREC format.

Now go back in Vivado, close the Hardware Manager and then make a power cycle to the board (disconnect the board from the USB, wait some seconds then attach the board again). The bootloader is able to start, due to some baud rate settings the output is messed up (I've to do some checking about this point), but when the data stop to came this means that the bitstream is configured, now press the BTN0 in the Cmod A7-35t to reset the MicroBlaze, the system should start to work properly (in my block design the reset input of the board is tied to the Clocking Wizard block).

after this first try seems that the SPI SREC bootloader actually implemented is only able to work as simple SPI not as quad spi, it would be nice if someone can also take a look to this matter.

Thanks and best regards.

[BYTEMAN]

To be more complete I've attached the Block Design pdf schematic.

Do you have some idea why the bootloader output is not clear with any baudarete between 9600 bps up to 115200 bps? The system is properly working but apparently the baudrate generated from the bootloader seems not correct. As application the baudarete is working properly at 9600 bps as is set into the AXI UartLite IP block:

the only trouble to have a clear output is related the bootloader.

Thanks and best regards.

design_1.pdf