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shashank0694

NetFPGA incorrect Ethernet PHY pins

Question

Hi,

I am working on NetFPGA - 1G CML board with Kintex-7 FPGA (xc7k325tffg676). The reference manual for the board specified a set of  pin numbers for the 4 Ethernet PHYs on the board, which is shown in the image attached. However, when I synthesized and implemented a small test design which gives inputs to Ethernet Lite IP core to be transmitted across PHY, I got the following error during implementation:

  • [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets phy_tx_clk_IBUF] > phy_tx_clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y214 and phy_tx_clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

On posting a query on Xilinx forums, I was told that pin  E13 is not a clock pin, whereas in the manual it is mentioned as phy_tx_clk. I was also directed to this link http://www.xilinx.com/support/packagefiles/k7packages/xc7k325tffg676pkg.txt, which gives the package pin specifications by xilinx. All clock inputs should be given on Clock Capable (CC) pins indicated by SRCC or MRCC. However none of the 4 PHY transmit clocks (B9,D14,J10,E13) are CC pins. I checked the board schematic, but it is the same as the reference manual.

I would be grateful to anyone who can guide me on what I should do to overcome this issue. 

Thanks.

 

Capture1.PNG

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3 answers to this question

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Hi, 

If that is a RGMII, that pin should be an output not an input. The best reference I have found for RGMII is http://www.hp.com/rnd/pdfs/RGMIIv1_3.pdf

Rather than muck about (or maybe more accurately "rather than actually learn") how output delays work, for my design, I generate it using a DDR register that is fed with a clock that is at 90 degrees to the main design's clock.

Some PHYs have the option to introduce a skew into the transmit clock,, and some designs achieve this though using a longer trace length for the clock line (this seems a bit dumb to me, but if needs must).

Mike

 

 

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Hi Mike,

Thanks a lot for the reply. So, if the txc pin is an output, I take it that it does not need to be a Clock Capable pin?

Also, which MAC core do you use/recommend? AXI Ethernet Lite is what I tried but that was before realising that it is not applicable for RGMII interface.

Thanks

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Here is the answer I got related to this subject.

TXC in the RGMII interface is generated by the MAC (FPGA), so it is indeed an output in the UCF.

Reference projects and IP libraries can be found at: https://github.com/NetFPGA/NetFPGA-public/wiki/Home_NetFPGA-1G-CML. For the Ethernet interface we recommend looking at: https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-nf1_cml_interface_v1_00_a

Please read "Licenses" chapter on the second link for details about Etherner intetrface licensing.

Write me if you need more information.

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