Use of two Pmod on ZedBoard

[Elie Assaf 3]

Hello.

I need to use two Pmod on ZedBoard. I already know how to communicate with one Pmod, by building a Vivado project with a Quad SPI IP in the block design, and than pin assigning it to a Pmod connector on the board.

Should I use two of such IPs? I tried but  I think what I did is wrong, since no connector is "active".

Thank you.

[D@n 364]

This might be a simpler solution: It suggests that the Zynq chip contains SPI ports and a SPI controller internal to the Zynq processor--you just need to enable them.  If true, you then wouldn't need the Quad SPI LogicCore from CoreGen at all.

Take a look at it,

Dan

[Elie Assaf 3]

Ciprian,

In fact I figured out a solution yesterday and it worked (can be used for two and only two PMods):

-Hardware (VIVADO): Use Zynq7 Processing system + AXI QSPI on JA + SPI1 (of the Processing system) on JE (MIO 10:15).

-Software (SDK): Initialisation and configuration of an XSpi (for the AXI QSPI), and a XSpiPs (for the PS SPI1), and enabling the SPI instance, transfer with it and then disabling it each time we want to use it. Note that the transfer is for sure done based on the reference manual of each PMod.

That was a solution of this problem.

But I'm still interested in knowing what was I misunderstanding? I may had think quite wrong in solving this problem. If I had to use multiple PMods, what would be the best solution? I know that an SPI controller can have many slaves. So how to implement and use an SPI interface where the master is the Zynq, and slaves are PMods, where all transfer with Pmods is software-based. When using 2 QSPIs, nothing worked and as D@N said that Vivado is confused. I don't really know how to use a QSPI with multiple slaves since only select slave is being extended to a vector, how can I connect MISO, MOSI and SCK to several Pmod connectors. The same was for PS SPIs with multiple slaves. When using PS SPI controllers with PL PMods, problems in transfer occurred (I guess because of the frequency difference between master and slave, so how to use PS SPI controllers with PL PMods). I think that I am missing something.

It would be great to have clear answers of above questions.

Thank you for being interested.

[D@n 364]

May I assume that if you use one of these the SPI port works?  And that both SPI ports will work with one of these if you just reassign pins?

If so, then your problem is simply getting both SPI port peripherals to work at the same time ... right?

Dan

[Elie Assaf 3]

In fact the problem is that if I use one SPI, any Pmod works. When I wanted to use two Pmods simultaneously, I thought that I have to use two SPIs in Vivado (I doubt that this would be the solution), so I did use two SPIs, added a constraints file to pin assign both SPIs to two Pmod connectors of the ZedBoard, but I noticed that no connector works (any Pmod does not work on any of the two Pmod connectors of the ZedBoard (even pin Vcc is at 0V for both connectors).

[Elie Assaf 3]

""In fact the problem is that if I use one SPI, any Pmod works": I mean that if I use on SPI and pin assign it to a Pmod connector of the ZedBoard, any Pmod works on the connector.

[D@n 364]

There's a fascinating discussion within the Quad SPI manual around page 48 or so.  I'm a bit concerned by the statement on page 49, "SPI pin are automatically generated through the Vivado Design Suite when interfacing  to an external SPI slave device."  That may be part of your problem: it expects you to use one SPI port, and multiple SPI Select (SS) lines, and your work to create multiple SPI ports is confusing Vivado.

Dan

[Elie Assaf 3]

Aha so you think I must use one SPI but with a number of slaves equal to 2?

[D@n 364]

That's one possibility.  I haven't found anything in the manual (yet) confirming it.

One quick question, though, are you using the STARTUPE primitive in both?  If so, that would be a violation since there is only one STARTUP SPI clock on the board.

Dan

[Elie Assaf 3]

No I'm not using this primitive of SPIs.

[Elie Assaf 3]

Should I do anything else than setting number of slaves of the SPI to 2, and assigning pin ss[1] to the ss pin of the second connector?

[D@n 364]

Well, actually it appears to be an option of the Quad SPI controller, not a second primitive.  The STARTUPE primitive offers access to the startup clock, which is often required to access the Quad SPI flash used to configure an FPGA at startup.  For example, on the Basys3 board I need to use the STARTUPE2 primitive to access the Quad SPI flash clock. 

Looking back at your other help requests, may I assume you are trying to use the PmodDA2 and PModAD1 to measure something, perform some operation, and then produce an analog output?  If you were to use these alternately, such as if they shared the same SPI port, your polling and output speed would be ... greatly diminished.  Is this acceptable to you, or shall we keep pushing for an alternate solution?

I guess what I'm getting at is that building a SPI controller in Verilog really isn't that hard.  You can find one such SPI controller here.  It's a part of a SPI flash controller, allowing me to read and write the configuration flash of a XuLA2 board.  You can also find the one for the SD-Card that I'm working on here (at the bottom of the file--the rest of the file is still a work in progress).  That one is also for the same board.  The design is made a touch more complicated than it otherwise needed to be because I have two SPI controllers fighting for the same SPI device. (Sort of like the Xilinx CoreGen primitive promises to do ...)  I'd point you at the SPI interface within my Quad SPI flash controller I've built as well, except ... I don't think you need or want the Quad SPI interaction, but just the basic SPI interaction.

Have you thought about creating your own SPI controller at all?  If you did, you could probably even guarantee that the two PMods, both A/D and D/A, were clocked using the same clock and timing ... I know that tends to be a tricky part of the mathematics for control systems.

Dan

[Elie Assaf 3]

Thank you Dan!

[Elie Assaf 3]

Is there a clear example of how to configure and use SPI PS in this final case? I think it's a bit different than controlling other SPI. The ss bits on the connectors have a 0 voltage.

[D@n 364]

Does this get you any closer to your quest for an example?

Dan

[Elie Assaf 3]

No it didn't,

I thought and tried to use SP0 of the PS with 2 SS: SS are working properly when setting slaves.But MISO and MOSI are the same for all slaves. Fortunately, I'm using Pmods that can either write or read, so I pin assigned MISO and MOSI properly (each on a pin of one of the two Pmod connectors of the board).

So SS are working properly, and sure GND and VCC are also well set.

But still, transfer is not proper. So I have 2 possibilities: either transfer is not done on proper pins (MISO and MOSI), or the CLK is not provided to Pmods (knowing that I assigned it to corresponding CLK pins at each connector).

Any clues for this situation?

Thank you.

[Elie Assaf 3]

Does anyone know how to make double connections of MISO, MOSI and SCK to the Pmod connectors (the slaves)?

[Ciprian 20]

Ok, so to recap... you tried to use 2 SPI controllers on 2 Pmod connectors and it did not work when you used them both in slave mode? As far as I understand you tried to use both the QSPI IP core and the PS SPI and that did not work either. You tried using only one controller and then changed the Pmod connector from the .xdc and it worked for all Pmod connectors, this means that the connectors are working and there is no problem with them.

Please correct me where I'm wrong

[D@n 364]

My apologies before beginning: I cannot offer you clear answers to your questions.  Sorry, I just don't know them.

What I do know, however, is that when the Xilinx IP doesn't do what you wish it to, you can always build your own IP.

Particularly for your problem, I would think you might find this valuable.  The Xilinx IP offers you no ability to control the timing of your SPI transactions.  As, if I recall correctly, you are trying to build a control loop, building a SPI port where you read from one SPI slave and wrote to another at the same time would be valuable.  Certainly from the standpoint of also presenting the control loop "math", it helps if you can produce an output synchronous with an input.  It also helps if you can guarantee an exact sample rate as I'm not sure anyone really understands control loop math when the sample rate isn't constant.

So let me ask: have you thought at all about dumping the Xilinx IP and building your own processing logic to accomplish these functions?

Dan