Does not load source files, circles and circles

[JSpar]

 

 

                                                                                        Dec. 23, 2021

Hello, 

  I recently posted a request for guidance on loading in my Nexys Artix-7 folder for doing Hardware Only demo.

  I picked up some other guidance from another user and I am following that now.

  I picked up Constraint file (XDC file) from Digilent I believe to be correct.

  I have also picked up a board file, created a new board file under it and loaded in a file, 
  from the Digilent GitHub, I believe to be correct for the csg324--100T system. 

  I've gotten to the point where It goes to load in the sources, again it circles and circles.

  I am wondering if the files are under the correct directory.

  Any guidance would be appreciated--getting good technical help is taking a lot longer,
  than even some of the most difficult apps I've had to deal with in the past.
  I have payed for help in the past, is someone available to help?

  The copyright ends in 2021--will support be continued and for how long?

Josh Sparber

 

 

 

[zygot]

I really have no idea what exactly it is that you are trying to do. Are you trying to implement a demo for your board? Can you be more specific? How is you project being created?

[JSpar]

 

                                                                                                                                                Jan. 17, 2022

Hi,

             

              I am trying to implement a demo, any demo, just to see if I can get the Arty-7 from Digilent working.

              I am following the file creation process step by step. What I found was that I needed to choose the Board tab in order
              to get the projects to the point where I can start creating source files.  Before that, it was just hanging and hanging. 

              So far, I have tried a Verilog file according from the Internet for blinking the LEDs. I obtained a constraint file from the Internet for this.
              For this I am following the Hardware Only project based on the download J. Colvin.            

             I have tried and I am trying a VHDL file based the Embedded Systems file by Jim Ledin.

             Neither of these yet works. 

             

           

J. Sparber

 

 

 

 

 

 

 

 

[JColvin]

Hi @JSpar,

Based on your other status post that included a picture of your constraints file, it appears that you did not uncomment the set_property line (line 7 in the Nexys A7 .xdc) for the clock, which is why you are getting the warning about too many positional options when parsing CLK100MHZ.

A picture and description of what needs to be done is in the last "section" of Adding a Constraint File section of the hardware only guide: https://digilent.com/reference/programmable-logic/guides/getting-started-with-vivado#adding_a_constraint_file.

Thanks,
JColvin