Unable to get UART working on existing Arty MicroBlaze solution

[rehsd]

Hi, everyone. I am looking for some guidance on how I could best troubleshoot an issue I'm running into. On my Arty, I can setup a new project with a MicroBlaze and UART, and I can write to the serial port from the MicroBlaze C code just fine. However, I have an existing MicroBlaze project where I am trying to add a UART, and I have been struggling to get output to the serial monitor.

I've posted some additional details here. Any suggestions on how to get the UART working in this existing project? What information can I provide to be more helpful?

Thank you!

[thinkthinkthink]

Check your UART interface with an ILA. This should be the first thing to do when debugging in Vivado.

[rehsd]

Thank you, @thinkthinkthink! I haven't used the Integrated Logic Analyzer IP before, but this looks to be a good time to try it out. ☺️ I'll dig into that next.

In the meantime, I found that the two UART pins aren't getting placed. The below image shows the results from a working project and a failing project. I haven't been able to find too much on the Netlist 29-160 Implementation error, yet, but I'm still looking.

 

 

[thinkthinkthink]

You can also try regenerating the bitstream after clearing IP cache from Tools->Settings->IP and/or manually constraining those pins in the board XDC file to your UART interface. It's pretty pointless to do any debugging if those pin connections haven't been made inside the FPGA. What I hope will happen is after you add an ILA to your design and regenerate the bitstream, Vivado will finally do its job properly during the synthesis and implementation phases.

Edited December 1, 2021 by thinkthinkthink

[rehsd]

I have regenerated the bitstream (along with the IP and other aspects of the project). I have tried the following in my board XDC (lines 91, 92), with no change in the placed pins, and with the subsequent error.

 

I also tried this:

Same Common 17-55 error and no change to the placed pins.

I also tried this:

Same Common 17-55 error and no change to the placed pins.

I then tried connecting the uartlite this way and received the subsequent error:

 

The connection approach above resulted in no changes to the placed pins.

Should I be trying to map the board pins a different way?

 

[thinkthinkthink]

Disconnect from the Board flow tab and try again with manual constraints.

Maybe it's also worth deleting the uartlite IP and adding it back again.

Edited December 1, 2021 by thinkthinkthink

[rehsd]

I disconnected the USB UART component from the Board tab and configured the ports and constraints as seen below. 

Same Common 17-55 error and no change to the placed pins.

I then removed the uartlite and added again (not from the Board tab, naming it _55).

 

Same Common 17-55 error and no change to the placed pins.

It seems that I'm not getting the right names in the constraint file for Vivado to figure out where to tie it to, hence the 17-55 error.

Most recently, I tried this (same results):

 

I will scour through the Warnings and see if I can find some additional clues.

Edited December 1, 2021 by rehsd

[rehsd]

I've noticed that the design wrapper isn't even getting the uartlite information in it (e.g., external ports), so I'll focus on the block design-to-design wrapper as where the issue lies. I'll post more details later today.

[rehsd]

@thinkthinkthink, thanks again for your helpful suggestions. I was able to resolve the issue. I had to delete the design wrapper and recreate it. Everything is working great now!