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PS and PL Communication


Fasih Ahmad

Question

Hi

I'm working Zebo board in my Final Year Project.

In the beginning, I'm required to communicate PS and PL of the board.

I'm required to take two integer in PS side of FPGA and send these two inputted integers to PL side and PL add these two integers and send sum back to the PS side. I saw many of the Youtube videos but failed to attempt. Will you please guide me a smart approach to solve this problem.

I have attached the image, which demonstrate visually what I exactly required.

 

PS_PL communication.PNG

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For the PS side you can use 2 XGpiops outputs and 1 Xgpiops input while on the PL side you'll have to either write your own VHDL/Verilog module that adds the 2 integers and outputs the sum into the Xgpiops input of the ZYNQ processing system or check if Xilinx offers IPs that perform additions/subtractions etc that come with your version of Vivado. 

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I suppose you could use the GPIO outputs, but the more general solution would be to build an AXI-lite peripheral.

Don't use the Vivado generated AXI-lite example.  It's broken.  You can have Vivado build the example for you, but if you do that then rip the guts out of it.  Replace it with something looking like this, and then you'll have a nicely working AXI-lite peripheral that you can do a lot of things with.

Once you have the basic AXI-lite slave up and running, you'll want to modify it with something like:

// Write to one of two registers

always @(posedge S_AXI_ACLK)
if (axil_write_ready)
begin
  case(skd_awaddr) // Assuming you left this as byte addressing ...
  0: reg_A <= skd_wdata;
  4: reg_B <= skd_wdata;
  endcase
end

// Read from either register, or their sum
always @(posedge S_AXI_ACLK)
if (axil_read_ready)
begin
  axil_read_data <= 0;
  case(skd_araddr)
  0: axil_read_data <= reg_A;
  4: axil_read_data <= reg_B;
  8: axil_read_data <= reg_A + reg_B;
  endcase
end

... or, at least, something like that.  It's been a while since I've looked at the specific register names to know that I got them right.  Bottom line, though, is that any good bus slave will have some kind of interaction roughly like that above, and a good AXI-lite slave is not really any different--once you get past the challenge of decoding AXI-lite in the first place.

Dan

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