Board Files for NI-Digilent Digital Systems Development Board (DSDB)

[Shaikh]

Hi . I have NI board designed by Digilent https://digilent.com/reference/dsdb/dsdb. This Digital Systems Development Board (DSDB) can be configured by Xilinx tools (VIVADO or ISE) and by labVIEW . Since the board comprises Zynq SOC, I want to configure PS ans PL of this board using XILINX tools only i.e.,  VIVADO 2020.1  and VITIS 2020.1. I am having a difficulty finding board files for this board. Any kind of help would be highly appreciated.

Thanks   

 

Edited November 24, 2021 by Shaikh

[elodg]

https://digilent.com/reference/dsdb/dsdb#design_resources

[Shaikh]

I know this link already. It does not the board files required by Viado and Vitis for hardware and software development. As far as I know Digilent has provided board files on this https://github.com/Digilent/vivado-boards?_ga=2.168069475.370165282.1637939739-2044605496.1637774448 Github repository for all of its boards . Unfortunately, this repos doesn't have the files for the DSDB board. 

[elodg]

The DSDB predates Vivado and board flow. You will have to make due with xdc and Zynq preset files. Board files bring a bit of convenience with the simplest of interfaces, but not by a lot.

[Abdul Rehman Buzdar]

Hi, using the .tcl preset file provided on the link https://digilent.com/reference/dsdb/dsdb , I am unable to print Hello world on on Vitis 2021, it is printing OK on any thing I print. I also have Zybo Z7-20 Board its working fine. I am able to control NI DSDB leds from Vitis SDK but unable to print on uart terminal. Please help?

 

Edited June 22, 2022 by Abdul Rehman Buzdar

[Tudor Roxana]

Hello ! 

When you want to integrate the UART you must be careful how you connect the signal taking in account the constraint file. 
In the DSDB constraint file the UART signals are declared using the following names : 
 -uart_rxd_out
 -uart_txd_in

If you follow your defined UART port you will see that the TXD signal is the output and the RXD is the input. The constraint file is giving you a hint with the suffixes "out" and "in". 
the "uart_rxd_out" is the RXD input of the PS that waits for your TXD output of the port and the "uart_txd_in" is the TXD output of your PS that will send data to the RXD input of your port. 

So if your External Interface is called UART_0_0, you should change the constraint file like this: 
- uart_rxd_out  becomes UART_0_0_txd
- uart_txd_in becomes UART_0_0_rxd

Are you careful to open a terminal emulator software ( like Putty or Tera Term) with the proper settings (Baud rate: 115200, 8 data bits, 1 stop bit, no parity bit), in order to see your results ?

I've tested a project on Vitis 2021.1, on a DSDB and is working properly. I will attach here the BOOT.BIN file. All you have to do is to :
1. Put the BOOT.BIN file on a Micro SD
2. Insert the Micro SD into connector J15 on the DSDB
2. Set SW8 to “SD”
3. Prepare your settings on the terminal software 
4. Turn board on and start the session of the terminal software 
5. You should see the following output on the terminal 

"Hello World
Successfully ran Hello World application"

If it still doesn't work. I can send you the whole Vitis workspace and the Vivado project in order to be able to see all my settings and configurations. 

Feel free to write again, if you still have problems in order to be able to provide you the solution.

BOOT.zip

[Abdul Rehman Buzdar]

Tudor Roxana, Thanks for the reply. Kindly share your Vitis workspace and the Vivado project. abdul.buzdar(at)gmail.com. 

Please guide about this step?

So if your External Interface is called UART_0_0, you should change the constraint file like this: 
- uart_rxd_out  becomes UART_0_0_txd
- uart_txd_in becomes UART_0_0_rxd

I added Zynq Processing System IP and added .tcl preset file of DSDB. How to add UART and make it external interface? Please guide 

Edited June 27, 2022 by Abdul Rehman Buzdar

[Tudor Roxana]

Hello, 

Regrading the external interface. When you open your block design in the left side you should see a tab called Design. 
When you expand the processing system you should see the following interfaces. 

If you right click on the UART_0_0 there should be the option "Make external". Click on that and now your block design should look like the example present in the second image. Now, in the Desing Tab you should see a new folder called External Interfaces where UART_0_0 should be present.

If you expand that you can see that you will have an input called UART_0_0_rxd and and output UART_0_0_txd. You will use them when you update your constraint file.
 

 

Edited July 5, 2022 by Tudor Roxana