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HI everybody,

Did anybody suceed to program CMOD S6 thanks to the JTAG header ?

I'm trying desperatly to initiate the JTAG chain without any success !

With I used the USB connexion, it works perfectly.

I wanted to try the platform cable USB from Xilinx to configure the FPGA like shown on the following picture :



I got the following error : 


There is something that "puzzles" me in the CMOD S6's schematic...

I put the parts of the schematic concerned by my interrogations in the attached file (PDF).

I noticed that there are physical links between J4 header, IC3A (Atmel) and IC5A (FPGA) for the following signals :




BUT regarding the TMS signal, there is a physical connexion only between the IC3A (Atmel) and the IC5A (FPGA).

On the J4 header, the signal that should be TMS, is called ISP-Reset. This signal is kept at 3.3V thanks a pull-up resistor and goes into the IC3D.

I used an oscilloscope to observe the TMS signal (during the Initalization JTAG chain phase) on IC5A (FPGA) in two different cases :

1°) by using the on board USB => the TMS signal changed

2°) by using the paltform Cable USB 2 => the ISP-reset signal changed BUT the TMS signal did not change...

In both the cases TDI-FPGA, TDO-FPGA and TCK changed

This could (maybe) explain why it is not possible to configure the FPGA directly by the JTAG header...

Does anyone have an explanation about this issue ?

Thanks a lot,

Kind regards,






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Unfortunately this 6 pin connector is not the JTAG connector, it is the programming connector for the microcontroller used to implement USB - JTAG solution.

So, you won't be able to use an external programmer to program the Spartan 6 FPGA on the Cmod S6.



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Depending on what you need, it is possible to reconfigure a board without the JTAG port.  For example, you could use one configuration to load a new configuration into the flash and then switch to it.  You could even control the first configuration and program the second via a UART port or ... gosh, just about any communication port you can connect to the CMod.  I've done this through UART, JTAG, and DEPP interfaces, so I know it can be done.  Indeed, the original plan for my CMod S6 SoC was to use the UART to do this.  In the end, the DEPP interface was just too easy to use, so I dropped the requirement to do reconfiguration via UART.


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When I worked on my CMod S6 SoC project, I used an open source "wishbone scope" to capture internals from the FPGA.  If you want to try this approach with your project, you could probably just use wbdeppsimple interface to create a very basic wishbone bus interface out of the DEPP controller to the scope, and thus be able to get and control a simple scope from within the chip.  I've got to believe Xilinx's solution isn't all that different from this ... although it is probably more configurable, and doesn't require wishbone access.

In my case, my needs were much more difficult: By the time I placed the CPU within the S6, I didn't have enough room left to talk to the PC except via UART.  Hence, when I was struggling with bugs, I would have the CPU always start by dumping what was in the scope (that piece of the solution is in ZipCPU assembly, so for your sake I won't link to it ...).  Hence, if the CPU I was working on crashed (which I could make happen by pressing a button), I could still get the scope contents (and CPU registers--but that's another story) to figure out how and why it had crashed.

The point being, there are other solutions aside and beyond chipscope.


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As it turns out, the Digilent USB does indeed support Chipscope. Just be sure to select "Digilent USB" in the JTAG menu in Chipscope and it runs.

Yes, it does take resources but it you have the room it's a nifty tool.

Your suggestions are good alternatives - If you're pin rich you can also just route signals you want to monitor out and record them with a logic analyzer which is particularly good if you need a deep trace.


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