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[DRC 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port refclk is Single-Ended but has an IOStandard of LVDS which can only support Differential

recently i bought Genesys2 kintex 7
I got this error...I want to blink LED. when clk signal matched with on board clock frequency...

 

Is there any example to work with clock frequency??

kindly share me

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Hello,

Please look at this forum thread. You can download the Genesys2 XDC from here. You can build a Vivado project using the code I attached in the older post and the XDC from our wiki. Let me know if you are having difficulties.

Sergiu 

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Don't you need to specify how many bits will be in your counter?  I'm not a VHDL type, but I would think that a different variable type would be required.  The Xilinx synthesis tool needs to know how many FPGA bits to use in order to implement your counter (27).  I don't think the natural number type you are using works for that purpose.

Dan

 

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Hello Dan thanks for your reply... My board supports LVDS and clock frequency is about 200Mhz so i want to slow down as 1hz at 1 second... can you re write the prgram and also contraint ?? 

 

 

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hello,

The constrains are commented. You'll have to uncomment them in order to work. 

This is how they look

## LEDs
##set_property PACKAGE_PIN T28 [get_ports S]
##set_property IOSTANDARD LVCMOS33 [get_ports S]
#set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1]
#set_property -dict { PACKAGE_PIN U30   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2]
#set_property -dict { PACKAGE_PIN U29   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3]
#set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4]
#set_property -dict { PACKAGE_PIN V26   IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L16P_T2_CSI_B_14 Sch=led[5]
#set_property -dict { PACKAGE_PIN W24   IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L20N_T3_A07_D23_14 Sch=led[6]
#set_property -dict { PACKAGE_PIN W23   IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L20P_T3_A08_D24_14 Sch=led[7]

 

and they should be looking like this: 

# LEDs
#set_property PACKAGE_PIN T28 [get_ports S]
#set_property IOSTANDARD LVCMOS33 [get_ports S]
set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1]
set_property -dict { PACKAGE_PIN U30   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2]
set_property -dict { PACKAGE_PIN U29   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3]
set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4]
set_property -dict { PACKAGE_PIN V26   IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L16P_T2_CSI_B_14 Sch=led[5]
set_property -dict { PACKAGE_PIN W24   IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L20N_T3_A07_D23_14 Sch=led[6]
set_property -dict { PACKAGE_PIN W23   IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L20P_T3_A08_D24_14 Sch=led[7]

 

If you want to blink all the leds, you'll have to declare "led" it as standard_logic_vector. Also, the name in the code must exactly match the name in the constraints. If you simply declare "led" it won't be recognized in the constraints as the signals are named led[1], led[2]. If you use a standard_logic_vector(7 downto 1) then you can refer to led[1] or led[2].

Uncomment just one line, name the signal led and see if it works.  The same thing with the clock signal. You'll have to uncomment the clock signal and give in the constraints the same name as in the code, otherwise it won't know where it should route signal and you'll get constraints errors. 

You can see the user demo project of the genesys 2 and take example from there: https://reference.digilentinc.com/genesys2/userdemo

Regards,

Bianca

 

 

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Hello hilarikas,

 

I just checked again your files and saw some things that I missed last time I looked. I saw that you tried to assign your clock signal and one led. Unfortunately you confused the XDC file with the UCF file.

Both UCF and XDC are contraints files. UCF is used with ISE and XDC is used with Vivado. The main difference between them is the syntax. What you tried to do was writing in the XDC the with the syntax from UCF. It won't work. 

XDC syntax for the clock:

## Clock Signal
#set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
#set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p

 

UCF syntax for the clock:

## Clock signal
#NET "clk"   LOC = "E3"    | IOSTANDARD = "LVCMOS33"; (taken from Nexys4 UCF)

What you tried to do:

##NET "refclk" LOC = "AD11";

 

Then, you cannot use the Genesys2 clock like this. It's a differential clock and you'll have to use a primitive to instantiate it. As you can see you have a sysclk_n and a sysclk_p. You'll have to use IBUFG primitive. you can find more information in Xilinx documentation. This primitive will allow you to use the clock. The primitive looks like this:

IBUFDS_inst : IBUFGDS
   generic map (
      DIFF_TERM => FALSE, -- Differential Termination 
      IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD => "DEFAULT")
   port map (
      O => O,  -- Buffer output
      I => I,  -- Diff_p buffer input (connect directly to top-level port)
      IB => IB -- Diff_n buffer input (connect directly to top-level port)
   );

Where, O is a clock signal you will declare as standard_logic. (Not Port, but Signal) in your case you wanted refclk and I and IB are the two parts of the differential clock. it would look like this:

IBUFDS_inst : IBUFGDS
   generic map (
      DIFF_TERM => FALSE, -- Differential Termination 
      IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD => "DEFAULT")
   port map (
      O => refclk,  -- Buffer output
      I => sysclk_p,  -- Diff_p buffer input (connect directly to top-level port)
      IB => sysclk_n -- Diff_n buffer input (connect directly to top-level port)
   );

After this when your code and your XDC are ready synthesize your project. Don't generate bitstream just synthesize then open the synthesized design. You'll have to assign that clock to the design, in order to know that is a clock signal.  Attached to this post is a word document with a tutorial on how to assign the clock.

At the end of this reload your XDC file. You'll have an option on the top where you have the page open and if all works well you'll see that it will add an extra line on the bottom of your XDC. Mine looks like this:

create_clock -period 5.000 -name sysclk_p -waveform {0.000 2.500} [get_ports sysclk_p]

After you finished, generate your bitstream and put it on the board. Attached here you'll also find an example of a working code that counts on the leds and the correct uncommented XDC file. 

Best regads,

Bianca

Asign Clock.docx

LED.vhd

Genesys2_H.xdc

Edited by Bianca

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